246 lines
6.2 KiB
C
246 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Driver for the Texas Instruments DP83TD510 PHY
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* Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
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*/
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#include <linux/bitfield.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#define DP83TD510E_PHY_ID 0x20000181
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/* MDIO_MMD_VEND2 registers */
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#define DP83TD510E_PHY_STS 0x10
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/* Bit 7 - mii_interrupt, active high. Clears on read.
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* Note: Clearing does not necessarily deactivate IRQ pin if interrupts pending.
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* This differs from the DP83TD510E datasheet (2020) which states this bit
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* clears on write 0.
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*/
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#define DP83TD510E_STS_MII_INT BIT(7)
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#define DP83TD510E_LINK_STATUS BIT(0)
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#define DP83TD510E_GEN_CFG 0x11
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#define DP83TD510E_GENCFG_INT_POLARITY BIT(3)
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#define DP83TD510E_GENCFG_INT_EN BIT(1)
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#define DP83TD510E_GENCFG_INT_OE BIT(0)
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#define DP83TD510E_INTERRUPT_REG_1 0x12
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#define DP83TD510E_INT1_LINK BIT(13)
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#define DP83TD510E_INT1_LINK_EN BIT(5)
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#define DP83TD510E_AN_STAT_1 0x60c
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#define DP83TD510E_MASTER_SLAVE_RESOL_FAIL BIT(15)
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#define DP83TD510E_MSE_DETECT 0xa85
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#define DP83TD510_SQI_MAX 7
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/* Register values are converted to SNR(dB) as suggested by
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* "Application Report - DP83TD510E Cable Diagnostics Toolkit":
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* SNR(dB) = -10 * log10 (VAL/2^17) - 1.76 dB.
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* SQI ranges are implemented according to "OPEN ALLIANCE - Advanced diagnostic
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* features for 100BASE-T1 automotive Ethernet PHYs"
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*/
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static const u16 dp83td510_mse_sqi_map[] = {
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0x0569, /* < 18dB */
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0x044c, /* 18dB =< SNR < 19dB */
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0x0369, /* 19dB =< SNR < 20dB */
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0x02b6, /* 20dB =< SNR < 21dB */
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0x0227, /* 21dB =< SNR < 22dB */
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0x01b6, /* 22dB =< SNR < 23dB */
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0x015b, /* 23dB =< SNR < 24dB */
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0x0000 /* 24dB =< SNR */
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};
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static int dp83td510_config_intr(struct phy_device *phydev)
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{
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int ret;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
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DP83TD510E_INTERRUPT_REG_1,
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DP83TD510E_INT1_LINK_EN);
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if (ret)
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return ret;
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ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
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DP83TD510E_GEN_CFG,
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DP83TD510E_GENCFG_INT_POLARITY |
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DP83TD510E_GENCFG_INT_EN |
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DP83TD510E_GENCFG_INT_OE);
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} else {
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
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DP83TD510E_INTERRUPT_REG_1, 0x0);
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if (ret)
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return ret;
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ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
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DP83TD510E_GEN_CFG,
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DP83TD510E_GENCFG_INT_EN);
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if (ret)
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return ret;
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}
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return ret;
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}
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static irqreturn_t dp83td510_handle_interrupt(struct phy_device *phydev)
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{
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int ret;
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/* Read the current enabled interrupts */
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1);
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if (ret < 0) {
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phy_error(phydev);
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return IRQ_NONE;
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} else if (!(ret & DP83TD510E_INT1_LINK_EN) ||
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!(ret & DP83TD510E_INT1_LINK)) {
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return IRQ_NONE;
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}
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phy_trigger_machine(phydev);
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return IRQ_HANDLED;
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}
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static int dp83td510_read_status(struct phy_device *phydev)
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{
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u16 phy_sts;
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int ret;
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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phydev->pause = 0;
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phydev->asym_pause = 0;
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linkmode_zero(phydev->lp_advertising);
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phy_sts = phy_read(phydev, DP83TD510E_PHY_STS);
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phydev->link = !!(phy_sts & DP83TD510E_LINK_STATUS);
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if (phydev->link) {
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/* This PHY supports only one link mode: 10BaseT1L_Full */
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phydev->duplex = DUPLEX_FULL;
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phydev->speed = SPEED_10;
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if (phydev->autoneg == AUTONEG_ENABLE) {
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ret = genphy_c45_read_lpa(phydev);
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if (ret)
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return ret;
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phy_resolve_aneg_linkmode(phydev);
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}
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}
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if (phydev->autoneg == AUTONEG_ENABLE) {
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ret = genphy_c45_baset1_read_status(phydev);
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if (ret < 0)
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return ret;
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
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DP83TD510E_AN_STAT_1);
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if (ret < 0)
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return ret;
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if (ret & DP83TD510E_MASTER_SLAVE_RESOL_FAIL)
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phydev->master_slave_state = MASTER_SLAVE_STATE_ERR;
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} else {
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return genphy_c45_pma_baset1_read_master_slave(phydev);
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}
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return 0;
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}
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static int dp83td510_config_aneg(struct phy_device *phydev)
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{
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bool changed = false;
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int ret;
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ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
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if (ret < 0)
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return ret;
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if (phydev->autoneg == AUTONEG_DISABLE)
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return genphy_c45_an_disable_aneg(phydev);
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ret = genphy_c45_an_config_aneg(phydev);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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return genphy_c45_check_and_restart_aneg(phydev, changed);
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}
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static int dp83td510_get_sqi(struct phy_device *phydev)
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{
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int sqi, ret;
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u16 mse_val;
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if (!phydev->link)
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return 0;
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT);
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if (ret < 0)
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return ret;
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mse_val = 0xFFFF & ret;
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for (sqi = 0; sqi < ARRAY_SIZE(dp83td510_mse_sqi_map); sqi++) {
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if (mse_val >= dp83td510_mse_sqi_map[sqi])
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return sqi;
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}
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return -EINVAL;
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}
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static int dp83td510_get_sqi_max(struct phy_device *phydev)
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{
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return DP83TD510_SQI_MAX;
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}
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static int dp83td510_get_features(struct phy_device *phydev)
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{
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/* This PHY can't respond on MDIO bus if no RMII clock is enabled.
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* In case RMII mode is used (most meaningful mode for this PHY) and
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* the PHY do not have own XTAL, and CLK providing MAC is not probed,
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* we won't be able to read all needed ability registers.
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* So provide it manually.
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*/
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linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
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phydev->supported);
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return 0;
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}
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static struct phy_driver dp83td510_driver[] = {
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{
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PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID),
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.name = "TI DP83TD510E",
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.config_aneg = dp83td510_config_aneg,
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.read_status = dp83td510_read_status,
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.get_features = dp83td510_get_features,
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.config_intr = dp83td510_config_intr,
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.handle_interrupt = dp83td510_handle_interrupt,
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.get_sqi = dp83td510_get_sqi,
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.get_sqi_max = dp83td510_get_sqi_max,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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} };
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module_phy_driver(dp83td510_driver);
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static struct mdio_device_id __maybe_unused dp83td510_tbl[] = {
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{ PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID) },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, dp83td510_tbl);
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MODULE_DESCRIPTION("Texas Instruments DP83TD510E PHY driver");
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MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
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MODULE_LICENSE("GPL v2");
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