1044 lines
27 KiB
C
1044 lines
27 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2021 Maxlinear Corporation
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* Copyright (C) 2020 Intel Corporation
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*
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* Drivers for Maxlinear Ethernet GPY
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*
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*/
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#include <linux/module.h>
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#include <linux/bitfield.h>
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#include <linux/hwmon.h>
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#include <linux/mutex.h>
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#include <linux/phy.h>
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#include <linux/polynomial.h>
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#include <linux/property.h>
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#include <linux/netdevice.h>
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/* PHY ID */
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#define PHY_ID_GPYx15B_MASK 0xFFFFFFFC
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#define PHY_ID_GPY21xB_MASK 0xFFFFFFF9
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#define PHY_ID_GPY2xx 0x67C9DC00
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#define PHY_ID_GPY115B 0x67C9DF00
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#define PHY_ID_GPY115C 0x67C9DF10
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#define PHY_ID_GPY211B 0x67C9DE08
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#define PHY_ID_GPY211C 0x67C9DE10
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#define PHY_ID_GPY212B 0x67C9DE09
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#define PHY_ID_GPY212C 0x67C9DE20
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#define PHY_ID_GPY215B 0x67C9DF04
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#define PHY_ID_GPY215C 0x67C9DF20
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#define PHY_ID_GPY241B 0x67C9DE40
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#define PHY_ID_GPY241BM 0x67C9DE80
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#define PHY_ID_GPY245B 0x67C9DEC0
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#define PHY_CTL1 0x13
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#define PHY_CTL1_MDICD BIT(3)
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#define PHY_CTL1_MDIAB BIT(2)
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#define PHY_CTL1_AMDIX BIT(0)
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#define PHY_MIISTAT 0x18 /* MII state */
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#define PHY_IMASK 0x19 /* interrupt mask */
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#define PHY_ISTAT 0x1A /* interrupt status */
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#define PHY_FWV 0x1E /* firmware version */
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#define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)
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#define PHY_MIISTAT_DPX BIT(3)
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#define PHY_MIISTAT_LS BIT(10)
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#define PHY_MIISTAT_SPD_10 0
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#define PHY_MIISTAT_SPD_100 1
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#define PHY_MIISTAT_SPD_1000 2
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#define PHY_MIISTAT_SPD_2500 4
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#define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
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#define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
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#define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
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#define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */
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#define PHY_IMASK_LSPC BIT(1) /* Link speed change */
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#define PHY_IMASK_LSTC BIT(0) /* Link state change */
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#define PHY_IMASK_MASK (PHY_IMASK_LSTC | \
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PHY_IMASK_LSPC | \
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PHY_IMASK_DXMC | \
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PHY_IMASK_ADSC | \
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PHY_IMASK_ANC)
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#define PHY_FWV_REL_MASK BIT(15)
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#define PHY_FWV_MAJOR_MASK GENMASK(11, 8)
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#define PHY_FWV_MINOR_MASK GENMASK(7, 0)
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#define PHY_PMA_MGBT_POLARITY 0x82
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#define PHY_MDI_MDI_X_MASK GENMASK(1, 0)
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#define PHY_MDI_MDI_X_NORMAL 0x3
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#define PHY_MDI_MDI_X_AB 0x2
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#define PHY_MDI_MDI_X_CD 0x1
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#define PHY_MDI_MDI_X_CROSS 0x0
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/* SGMII */
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#define VSPEC1_SGMII_CTRL 0x08
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#define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */
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#define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */
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#define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \
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VSPEC1_SGMII_CTRL_ANRS)
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/* Temperature sensor */
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#define VSPEC1_TEMP_STA 0x0E
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#define VSPEC1_TEMP_STA_DATA GENMASK(9, 0)
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/* Mailbox */
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#define VSPEC1_MBOX_DATA 0x5
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#define VSPEC1_MBOX_ADDRLO 0x6
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#define VSPEC1_MBOX_CMD 0x7
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#define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0)
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#define VSPEC1_MBOX_CMD_RD (0 << 8)
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#define VSPEC1_MBOX_CMD_READY BIT(15)
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/* WoL */
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#define VPSPEC2_WOL_CTL 0x0E06
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#define VPSPEC2_WOL_AD01 0x0E08
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#define VPSPEC2_WOL_AD23 0x0E09
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#define VPSPEC2_WOL_AD45 0x0E0A
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#define WOL_EN BIT(0)
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/* Internal registers, access via mbox */
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#define REG_GPIO0_OUT 0xd3ce00
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struct gpy_priv {
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/* serialize mailbox acesses */
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struct mutex mbox_lock;
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u8 fw_major;
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u8 fw_minor;
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/* It takes 3 seconds to fully switch out of loopback mode before
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* it can safely re-enter loopback mode. Record the time when
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* loopback is disabled. Check and wait if necessary before loopback
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* is enabled.
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*/
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u64 lb_dis_to;
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};
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static const struct {
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int major;
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int minor;
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} ver_need_sgmii_reaneg[] = {
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{7, 0x6D},
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{8, 0x6D},
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{9, 0x73},
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};
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#if IS_ENABLED(CONFIG_HWMON)
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/* The original translation formulae of the temperature (in degrees of Celsius)
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* are as follows:
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*
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* T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
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* 3.0762e-1*(N^1) + -5.2156e1
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*
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* where [-52.156, 137.961]C and N = [0, 1023].
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*
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* They must be accordingly altered to be suitable for the integer arithmetics.
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* The technique is called 'factor redistribution', which just makes sure the
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* multiplications and divisions are made so to have a result of the operations
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* within the integer numbers limit. In addition we need to translate the
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* formulae to accept millidegrees of Celsius. Here what it looks like after
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* the alterations:
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*
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* T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) +
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* 307620e-3*(N^1) + -52156
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*
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* where T = [-52156, 137961]mC and N = [0, 1023].
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*/
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static const struct polynomial poly_N_to_temp = {
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.terms = {
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{4, -25761, 1000, 1},
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{3, 97332, 1000, 1},
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{2, -191650, 1000, 1},
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{1, 307620, 1000, 1},
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{0, -52156, 1, 1}
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}
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};
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static int gpy_hwmon_read(struct device *dev,
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enum hwmon_sensor_types type,
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u32 attr, int channel, long *value)
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{
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struct phy_device *phydev = dev_get_drvdata(dev);
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int ret;
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
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if (ret < 0)
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return ret;
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if (!ret)
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return -ENODATA;
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*value = polynomial_calc(&poly_N_to_temp,
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FIELD_GET(VSPEC1_TEMP_STA_DATA, ret));
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return 0;
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}
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static umode_t gpy_hwmon_is_visible(const void *data,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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return 0444;
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}
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static const struct hwmon_channel_info * const gpy_hwmon_info[] = {
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HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
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NULL
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};
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static const struct hwmon_ops gpy_hwmon_hwmon_ops = {
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.is_visible = gpy_hwmon_is_visible,
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.read = gpy_hwmon_read,
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};
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static const struct hwmon_chip_info gpy_hwmon_chip_info = {
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.ops = &gpy_hwmon_hwmon_ops,
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.info = gpy_hwmon_info,
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};
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static int gpy_hwmon_register(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct device *hwmon_dev;
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char *hwmon_name;
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hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
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if (IS_ERR(hwmon_name))
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return PTR_ERR(hwmon_name);
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hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
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phydev,
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&gpy_hwmon_chip_info,
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NULL);
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return PTR_ERR_OR_ZERO(hwmon_dev);
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}
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#else
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static int gpy_hwmon_register(struct phy_device *phydev)
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{
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return 0;
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}
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#endif
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static int gpy_mbox_read(struct phy_device *phydev, u32 addr)
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{
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struct gpy_priv *priv = phydev->priv;
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int val, ret;
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u16 cmd;
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mutex_lock(&priv->mbox_lock);
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
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addr);
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if (ret)
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goto out;
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cmd = VSPEC1_MBOX_CMD_RD;
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cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16);
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
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if (ret)
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goto out;
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/* The mbox read is used in the interrupt workaround. It was observed
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* that a read might take up to 2.5ms. This is also the time for which
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* the interrupt line is stuck low. To be on the safe side, poll the
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* ready bit for 10ms.
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*/
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ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
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VSPEC1_MBOX_CMD, val,
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(val & VSPEC1_MBOX_CMD_READY),
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500, 10000, false);
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if (ret)
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goto out;
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
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out:
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mutex_unlock(&priv->mbox_lock);
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return ret;
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}
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static int gpy_config_init(struct phy_device *phydev)
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{
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int ret;
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/* Mask all interrupts */
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ret = phy_write(phydev, PHY_IMASK, 0);
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if (ret)
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return ret;
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/* Clear all pending interrupts */
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ret = phy_read(phydev, PHY_ISTAT);
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return ret < 0 ? ret : 0;
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}
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static int gpy_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct gpy_priv *priv;
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int fw_version;
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int ret;
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if (!phydev->is_c45) {
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ret = phy_get_c45_ids(phydev);
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if (ret < 0)
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return ret;
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}
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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phydev->priv = priv;
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mutex_init(&priv->mbox_lock);
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if (!device_property_present(dev, "maxlinear,use-broken-interrupts"))
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phydev->dev_flags |= PHY_F_NO_IRQ;
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fw_version = phy_read(phydev, PHY_FWV);
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if (fw_version < 0)
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return fw_version;
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priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version);
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priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version);
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ret = gpy_hwmon_register(phydev);
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if (ret)
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return ret;
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/* Show GPY PHY FW version in dmesg */
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phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n",
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priv->fw_major, priv->fw_minor, fw_version,
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fw_version & PHY_FWV_REL_MASK ? "" : " test version");
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return 0;
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}
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static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
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{
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struct gpy_priv *priv = phydev->priv;
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size_t i;
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for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
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if (priv->fw_major != ver_need_sgmii_reaneg[i].major)
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continue;
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if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor)
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return true;
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break;
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}
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return false;
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}
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static bool gpy_2500basex_chk(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read(phydev, PHY_MIISTAT);
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if (ret < 0) {
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phydev_err(phydev, "Error: MDIO register access failed: %d\n",
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ret);
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return false;
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}
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if (!(ret & PHY_MIISTAT_LS) ||
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FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
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return false;
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phydev->speed = SPEED_2500;
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phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
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VSPEC1_SGMII_CTRL_ANEN, 0);
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return true;
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}
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static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
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if (ret < 0) {
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phydev_err(phydev, "Error: MMD register access failed: %d\n",
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ret);
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return true;
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}
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return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
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}
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static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl)
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{
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int ret;
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u16 val;
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switch (ctrl) {
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case ETH_TP_MDI_AUTO:
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val = PHY_CTL1_AMDIX;
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break;
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case ETH_TP_MDI_X:
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val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD);
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break;
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case ETH_TP_MDI:
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val = 0;
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break;
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default:
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return 0;
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}
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ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB |
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PHY_CTL1_MDICD, val);
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if (ret < 0)
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return ret;
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return genphy_c45_restart_aneg(phydev);
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}
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static int gpy_config_aneg(struct phy_device *phydev)
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{
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bool changed = false;
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u32 adv;
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int ret;
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if (phydev->autoneg == AUTONEG_DISABLE) {
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/* Configure half duplex with genphy_setup_forced,
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* because genphy_c45_pma_setup_forced does not support.
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*/
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return phydev->duplex != DUPLEX_FULL
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? genphy_setup_forced(phydev)
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: genphy_c45_pma_setup_forced(phydev);
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}
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ret = gpy_config_mdix(phydev, phydev->mdix_ctrl);
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if (ret < 0)
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return ret;
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ret = genphy_c45_an_config_aneg(phydev);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
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ret = phy_modify_changed(phydev, MII_CTRL1000,
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ADVERTISE_1000FULL | ADVERTISE_1000HALF,
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adv);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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ret = genphy_c45_check_and_restart_aneg(phydev, changed);
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if (ret < 0)
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return ret;
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if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
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phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
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return 0;
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/* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
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* disabled.
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*/
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if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
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!gpy_sgmii_aneg_en(phydev))
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return 0;
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/* There is a design constraint in GPY2xx device where SGMII AN is
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* only triggered when there is change of speed. If, PHY link
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* partner`s speed is still same even after PHY TPI is down and up
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* again, SGMII AN is not triggered and hence no new in-band message
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* from GPY to MAC side SGMII.
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* This could cause an issue during power up, when PHY is up prior to
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* MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
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* wouldn`t receive new in-band message from GPY with correct link
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* status, speed and duplex info.
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*
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* 1) If PHY is already up and TPI link status is still down (such as
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* hard reboot), TPI link status is polled for 4 seconds before
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* retriggerring SGMII AN.
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* 2) If PHY is already up and TPI link status is also up (such as soft
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* reboot), polling of TPI link status is not needed and SGMII AN is
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* immediately retriggered.
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* 3) Other conditions such as PHY is down, speed change etc, skip
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* retriggering SGMII AN. Note: in case of speed change, GPY FW will
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* initiate SGMII AN.
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*/
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if (phydev->state != PHY_UP)
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return 0;
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ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
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20000, 4000000, false);
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if (ret == -ETIMEDOUT)
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return 0;
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else if (ret < 0)
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return ret;
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/* Trigger SGMII AN. */
|
|
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
|
VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
|
|
}
|
|
|
|
static int gpy_update_mdix(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
ret = phy_read(phydev, PHY_CTL1);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (ret & PHY_CTL1_AMDIX)
|
|
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
|
|
else
|
|
if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB)
|
|
phydev->mdix_ctrl = ETH_TP_MDI_X;
|
|
else
|
|
phydev->mdix_ctrl = ETH_TP_MDI;
|
|
|
|
ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL)
|
|
phydev->mdix = ETH_TP_MDI_X;
|
|
else
|
|
phydev->mdix = ETH_TP_MDI;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gpy_update_interface(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
/* Interface mode is fixed for USXGMII and integrated PHY */
|
|
if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
|
|
phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
|
|
return -EINVAL;
|
|
|
|
/* Automatically switch SERDES interface between SGMII and 2500-BaseX
|
|
* according to speed. Disable ANEG in 2500-BaseX mode.
|
|
*/
|
|
switch (phydev->speed) {
|
|
case SPEED_2500:
|
|
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
|
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
|
VSPEC1_SGMII_CTRL_ANEN, 0);
|
|
if (ret < 0) {
|
|
phydev_err(phydev,
|
|
"Error: Disable of SGMII ANEG failed: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
break;
|
|
case SPEED_1000:
|
|
case SPEED_100:
|
|
case SPEED_10:
|
|
phydev->interface = PHY_INTERFACE_MODE_SGMII;
|
|
if (gpy_sgmii_aneg_en(phydev))
|
|
break;
|
|
/* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
|
|
* if ANEG is disabled (in 2500-BaseX mode).
|
|
*/
|
|
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
|
VSPEC1_SGMII_ANEN_ANRS,
|
|
VSPEC1_SGMII_ANEN_ANRS);
|
|
if (ret < 0) {
|
|
phydev_err(phydev,
|
|
"Error: Enable of SGMII ANEG failed: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) {
|
|
ret = genphy_read_master_slave(phydev);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
return gpy_update_mdix(phydev);
|
|
}
|
|
|
|
static int gpy_read_status(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
ret = genphy_update_link(phydev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
phydev->speed = SPEED_UNKNOWN;
|
|
phydev->duplex = DUPLEX_UNKNOWN;
|
|
phydev->pause = 0;
|
|
phydev->asym_pause = 0;
|
|
|
|
if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
|
|
ret = genphy_c45_read_lpa(phydev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Read the link partner's 1G advertisement */
|
|
ret = phy_read(phydev, MII_STAT1000);
|
|
if (ret < 0)
|
|
return ret;
|
|
mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
|
|
} else if (phydev->autoneg == AUTONEG_DISABLE) {
|
|
linkmode_zero(phydev->lp_advertising);
|
|
}
|
|
|
|
ret = phy_read(phydev, PHY_MIISTAT);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
|
|
phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
|
|
switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) {
|
|
case PHY_MIISTAT_SPD_10:
|
|
phydev->speed = SPEED_10;
|
|
break;
|
|
case PHY_MIISTAT_SPD_100:
|
|
phydev->speed = SPEED_100;
|
|
break;
|
|
case PHY_MIISTAT_SPD_1000:
|
|
phydev->speed = SPEED_1000;
|
|
break;
|
|
case PHY_MIISTAT_SPD_2500:
|
|
phydev->speed = SPEED_2500;
|
|
break;
|
|
}
|
|
|
|
if (phydev->link) {
|
|
ret = gpy_update_interface(phydev);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gpy_config_intr(struct phy_device *phydev)
|
|
{
|
|
u16 mask = 0;
|
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
|
mask = PHY_IMASK_MASK;
|
|
|
|
return phy_write(phydev, PHY_IMASK, mask);
|
|
}
|
|
|
|
static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev)
|
|
{
|
|
int reg;
|
|
|
|
reg = phy_read(phydev, PHY_ISTAT);
|
|
if (reg < 0) {
|
|
phy_error(phydev);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
if (!(reg & PHY_IMASK_MASK))
|
|
return IRQ_NONE;
|
|
|
|
/* The PHY might leave the interrupt line asserted even after PHY_ISTAT
|
|
* is read. To avoid interrupt storms, delay the interrupt handling as
|
|
* long as the PHY drives the interrupt line. An internal bus read will
|
|
* stall as long as the interrupt line is asserted, thus just read a
|
|
* random register here.
|
|
* Because we cannot access the internal bus at all while the interrupt
|
|
* is driven by the PHY, there is no way to make the interrupt line
|
|
* unstuck (e.g. by changing the pinmux to GPIO input) during that time
|
|
* frame. Therefore, polling is the best we can do and won't do any more
|
|
* harm.
|
|
* It was observed that this bug happens on link state and link speed
|
|
* changes independent of the firmware version.
|
|
*/
|
|
if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) {
|
|
reg = gpy_mbox_read(phydev, REG_GPIO0_OUT);
|
|
if (reg < 0) {
|
|
phy_error(phydev);
|
|
return IRQ_NONE;
|
|
}
|
|
}
|
|
|
|
phy_trigger_machine(phydev);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int gpy_set_wol(struct phy_device *phydev,
|
|
struct ethtool_wolinfo *wol)
|
|
{
|
|
struct net_device *attach_dev = phydev->attached_dev;
|
|
int ret;
|
|
|
|
if (wol->wolopts & WAKE_MAGIC) {
|
|
/* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5
|
|
* VPSPEC2_WOL_AD45 = Byte0:Byte1
|
|
* VPSPEC2_WOL_AD23 = Byte2:Byte3
|
|
* VPSPEC2_WOL_AD01 = Byte4:Byte5
|
|
*/
|
|
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
|
|
VPSPEC2_WOL_AD45,
|
|
((attach_dev->dev_addr[0] << 8) |
|
|
attach_dev->dev_addr[1]));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
|
|
VPSPEC2_WOL_AD23,
|
|
((attach_dev->dev_addr[2] << 8) |
|
|
attach_dev->dev_addr[3]));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
|
|
VPSPEC2_WOL_AD01,
|
|
((attach_dev->dev_addr[4] << 8) |
|
|
attach_dev->dev_addr[5]));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Enable the WOL interrupt */
|
|
ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Enable magic packet matching */
|
|
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
|
|
VPSPEC2_WOL_CTL,
|
|
WOL_EN);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Clear the interrupt status register.
|
|
* Only WoL is enabled so clear all.
|
|
*/
|
|
ret = phy_read(phydev, PHY_ISTAT);
|
|
if (ret < 0)
|
|
return ret;
|
|
} else {
|
|
/* Disable magic packet matching */
|
|
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
|
|
VPSPEC2_WOL_CTL,
|
|
WOL_EN);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
if (wol->wolopts & WAKE_PHY) {
|
|
/* Enable the link state change interrupt */
|
|
ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Clear the interrupt status register */
|
|
ret = phy_read(phydev, PHY_ISTAT);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC))
|
|
phy_trigger_machine(phydev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Disable the link state change interrupt */
|
|
return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
|
|
}
|
|
|
|
static void gpy_get_wol(struct phy_device *phydev,
|
|
struct ethtool_wolinfo *wol)
|
|
{
|
|
int ret;
|
|
|
|
wol->supported = WAKE_MAGIC | WAKE_PHY;
|
|
wol->wolopts = 0;
|
|
|
|
ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL);
|
|
if (ret & WOL_EN)
|
|
wol->wolopts |= WAKE_MAGIC;
|
|
|
|
ret = phy_read(phydev, PHY_IMASK);
|
|
if (ret & PHY_IMASK_LSTC)
|
|
wol->wolopts |= WAKE_PHY;
|
|
}
|
|
|
|
static int gpy_loopback(struct phy_device *phydev, bool enable)
|
|
{
|
|
struct gpy_priv *priv = phydev->priv;
|
|
u16 set = 0;
|
|
int ret;
|
|
|
|
if (enable) {
|
|
u64 now = get_jiffies_64();
|
|
|
|
/* wait until 3 seconds from last disable */
|
|
if (time_before64(now, priv->lb_dis_to))
|
|
msleep(jiffies64_to_msecs(priv->lb_dis_to - now));
|
|
|
|
set = BMCR_LOOPBACK;
|
|
}
|
|
|
|
ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set);
|
|
if (ret <= 0)
|
|
return ret;
|
|
|
|
if (enable) {
|
|
/* It takes some time for PHY device to switch into
|
|
* loopback mode.
|
|
*/
|
|
msleep(100);
|
|
} else {
|
|
priv->lb_dis_to = get_jiffies_64() + HZ * 3;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gpy115_loopback(struct phy_device *phydev, bool enable)
|
|
{
|
|
struct gpy_priv *priv = phydev->priv;
|
|
|
|
if (enable)
|
|
return gpy_loopback(phydev, enable);
|
|
|
|
if (priv->fw_minor > 0x76)
|
|
return gpy_loopback(phydev, 0);
|
|
|
|
return genphy_soft_reset(phydev);
|
|
}
|
|
|
|
static struct phy_driver gpy_drivers[] = {
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx),
|
|
.name = "Maxlinear Ethernet GPY2xx",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy_loopback,
|
|
},
|
|
{
|
|
.phy_id = PHY_ID_GPY115B,
|
|
.phy_id_mask = PHY_ID_GPYx15B_MASK,
|
|
.name = "Maxlinear Ethernet GPY115B",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy115_loopback,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_GPY115C),
|
|
.name = "Maxlinear Ethernet GPY115C",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy115_loopback,
|
|
},
|
|
{
|
|
.phy_id = PHY_ID_GPY211B,
|
|
.phy_id_mask = PHY_ID_GPY21xB_MASK,
|
|
.name = "Maxlinear Ethernet GPY211B",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy_loopback,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_GPY211C),
|
|
.name = "Maxlinear Ethernet GPY211C",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy_loopback,
|
|
},
|
|
{
|
|
.phy_id = PHY_ID_GPY212B,
|
|
.phy_id_mask = PHY_ID_GPY21xB_MASK,
|
|
.name = "Maxlinear Ethernet GPY212B",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy_loopback,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_GPY212C),
|
|
.name = "Maxlinear Ethernet GPY212C",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy_loopback,
|
|
},
|
|
{
|
|
.phy_id = PHY_ID_GPY215B,
|
|
.phy_id_mask = PHY_ID_GPYx15B_MASK,
|
|
.name = "Maxlinear Ethernet GPY215B",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy_loopback,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_GPY215C),
|
|
.name = "Maxlinear Ethernet GPY215C",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy_loopback,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_GPY241B),
|
|
.name = "Maxlinear Ethernet GPY241B",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy_loopback,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM),
|
|
.name = "Maxlinear Ethernet GPY241BM",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy_loopback,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_GPY245B),
|
|
.name = "Maxlinear Ethernet GPY245B",
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_init = gpy_config_init,
|
|
.probe = gpy_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.config_aneg = gpy_config_aneg,
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.read_status = gpy_read_status,
|
|
.config_intr = gpy_config_intr,
|
|
.handle_interrupt = gpy_handle_interrupt,
|
|
.set_wol = gpy_set_wol,
|
|
.get_wol = gpy_get_wol,
|
|
.set_loopback = gpy_loopback,
|
|
},
|
|
};
|
|
module_phy_driver(gpy_drivers);
|
|
|
|
static struct mdio_device_id __maybe_unused gpy_tbl[] = {
|
|
{PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)},
|
|
{PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK},
|
|
{PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)},
|
|
{PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK},
|
|
{PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)},
|
|
{PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK},
|
|
{PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)},
|
|
{PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK},
|
|
{PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)},
|
|
{PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)},
|
|
{PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)},
|
|
{PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(mdio, gpy_tbl);
|
|
|
|
MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver");
|
|
MODULE_AUTHOR("Xu Liang");
|
|
MODULE_LICENSE("GPL");
|