161 lines
4.8 KiB
C
161 lines
4.8 KiB
C
// SPDX-License-Identifier: BSD-3-Clause-Clear
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/*
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* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "hal_desc.h"
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#include "hal.h"
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#include "hal_tx.h"
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#include "hif.h"
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#define DSCP_TID_MAP_TBL_ENTRY_SIZE 64
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/* dscp_tid_map - Default DSCP-TID mapping
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*
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* DSCP TID
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* 000000 0
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* 001000 1
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* 010000 2
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* 011000 3
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* 100000 4
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* 101000 5
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* 110000 6
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* 111000 7
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*/
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static const u8 dscp_tid_map[DSCP_TID_MAP_TBL_ENTRY_SIZE] = {
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0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 1,
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2, 2, 2, 2, 2, 2, 2, 2,
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3, 3, 3, 3, 3, 3, 3, 3,
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4, 4, 4, 4, 4, 4, 4, 4,
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5, 5, 5, 5, 5, 5, 5, 5,
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6, 6, 6, 6, 6, 6, 6, 6,
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7, 7, 7, 7, 7, 7, 7, 7,
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};
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void ath11k_hal_tx_cmd_desc_setup(struct ath11k_base *ab, void *cmd,
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struct hal_tx_info *ti)
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{
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struct hal_tcl_data_cmd *tcl_cmd = (struct hal_tcl_data_cmd *)cmd;
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tcl_cmd->buf_addr_info.info0 =
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FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr);
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tcl_cmd->buf_addr_info.info1 =
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FIELD_PREP(BUFFER_ADDR_INFO1_ADDR,
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((uint64_t)ti->paddr >> HAL_ADDR_MSB_REG_SHIFT));
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tcl_cmd->buf_addr_info.info1 |=
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FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, ti->rbm_id) |
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FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id);
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tcl_cmd->info0 =
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE,
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ti->encrypt_type) |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE,
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ti->search_type) |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN,
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ti->addr_search_flags) |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM,
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ti->meta_data_flags);
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tcl_cmd->info1 = ti->flags0 |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_DATA_LEN, ti->data_len) |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET, ti->pkt_offset);
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tcl_cmd->info2 = ti->flags1 |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID, ti->tid) |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_LMAC_ID, ti->lmac_id);
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tcl_cmd->info3 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX,
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ti->dscp_tid_tbl_idx) |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX,
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ti->bss_ast_idx) |
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FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM,
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ti->bss_ast_hash);
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tcl_cmd->info4 = 0;
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if (ti->enable_mesh)
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ab->hw_params.hw_ops->tx_mesh_enable(ab, tcl_cmd);
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}
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void ath11k_hal_tx_set_dscp_tid_map(struct ath11k_base *ab, int id)
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{
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u32 ctrl_reg_val;
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u32 addr;
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u8 hw_map_val[HAL_DSCP_TID_TBL_SIZE];
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int i;
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u32 value;
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int cnt = 0;
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ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
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HAL_TCL1_RING_CMN_CTRL_REG);
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/* Enable read/write access */
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ctrl_reg_val |= HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
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ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
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HAL_TCL1_RING_CMN_CTRL_REG, ctrl_reg_val);
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addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP +
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(4 * id * (HAL_DSCP_TID_TBL_SIZE / 4));
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/* Configure each DSCP-TID mapping in three bits there by configure
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* three bytes in an iteration.
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*/
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for (i = 0; i < DSCP_TID_MAP_TBL_ENTRY_SIZE; i += 8) {
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value = FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP0,
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dscp_tid_map[i]) |
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FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP1,
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dscp_tid_map[i + 1]) |
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FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP2,
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dscp_tid_map[i + 2]) |
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FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP3,
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dscp_tid_map[i + 3]) |
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FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP4,
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dscp_tid_map[i + 4]) |
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FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP5,
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dscp_tid_map[i + 5]) |
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FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP6,
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dscp_tid_map[i + 6]) |
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FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP7,
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dscp_tid_map[i + 7]);
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memcpy(&hw_map_val[cnt], (u8 *)&value, 3);
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cnt += 3;
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}
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for (i = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 4) {
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ath11k_hif_write32(ab, addr, *(u32 *)&hw_map_val[i]);
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addr += 4;
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}
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/* Disable read/write access */
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ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
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HAL_TCL1_RING_CMN_CTRL_REG);
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ctrl_reg_val &= ~HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
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ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
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HAL_TCL1_RING_CMN_CTRL_REG,
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ctrl_reg_val);
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}
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void ath11k_hal_tx_init_data_ring(struct ath11k_base *ab, struct hal_srng *srng)
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{
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struct hal_srng_params params;
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struct hal_tlv_hdr *tlv;
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int i, entry_size;
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u8 *desc;
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memset(¶ms, 0, sizeof(params));
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entry_size = ath11k_hal_srng_get_entrysize(ab, HAL_TCL_DATA);
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ath11k_hal_srng_get_params(ab, srng, ¶ms);
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desc = (u8 *)params.ring_base_vaddr;
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for (i = 0; i < params.num_entries; i++) {
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tlv = (struct hal_tlv_hdr *)desc;
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tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_TCL_DATA_CMD) |
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FIELD_PREP(HAL_TLV_HDR_LEN,
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sizeof(struct hal_tcl_data_cmd));
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desc += entry_size;
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}
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}
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