305 lines
11 KiB
C
305 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* Copyright (C) 2018, 2020-2022 Intel Corporation
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*/
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#ifndef __iwl_context_info_file_gen3_h__
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#define __iwl_context_info_file_gen3_h__
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#include "iwl-context-info.h"
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#define CSR_CTXT_INFO_BOOT_CTRL 0x0
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#define CSR_CTXT_INFO_ADDR 0x118
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#define CSR_IML_DATA_ADDR 0x120
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#define CSR_IML_SIZE_ADDR 0x128
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#define CSR_IML_RESP_ADDR 0x12c
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#define UNFRAGMENTED_PNVM_PAYLOADS_NUMBER 2
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/* Set bit for enabling automatic function boot */
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#define CSR_AUTO_FUNC_BOOT_ENA BIT(1)
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/* Set bit for initiating function boot */
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#define CSR_AUTO_FUNC_INIT BIT(7)
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/**
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* enum iwl_prph_scratch_mtr_format - tfd size configuration
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* @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd
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* @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd
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* @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd
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* @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd
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*/
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enum iwl_prph_scratch_mtr_format {
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IWL_PRPH_MTR_FORMAT_16B = 0x0,
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IWL_PRPH_MTR_FORMAT_32B = 0x40000,
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IWL_PRPH_MTR_FORMAT_64B = 0x80000,
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IWL_PRPH_MTR_FORMAT_256B = 0xC0000,
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};
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/**
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* enum iwl_prph_scratch_flags - PRPH scratch control flags
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* @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug
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* @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf
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* @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated
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* in hwm config.
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* @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM
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* @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for
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* multicomm.
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* @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW
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* @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K)
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* @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for
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* completion descriptor, 1 for responses (legacy)
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* @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd.
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* There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit,
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* 3: 256 bit.
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* @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored
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* by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K
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* appropriately; use the below values for this.
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* @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size
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* @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size
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* @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size
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*/
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enum iwl_prph_scratch_flags {
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IWL_PRPH_SCRATCH_IMR_DEBUG_EN = BIT(1),
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IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4),
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IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8),
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IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9),
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IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10),
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IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11),
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IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16),
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IWL_PRPH_SCRATCH_MTR_MODE = BIT(17),
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IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19),
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IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20,
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IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20,
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IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20,
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IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20,
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};
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/*
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* struct iwl_prph_scratch_version - version structure
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* @mac_id: SKU and revision id
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* @version: prph scratch information version id
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* @size: the size of the context information in DWs
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* @reserved: reserved
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*/
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struct iwl_prph_scratch_version {
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__le16 mac_id;
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__le16 version;
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__le16 size;
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__le16 reserved;
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} __packed; /* PERIPH_SCRATCH_VERSION_S */
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/*
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* struct iwl_prph_scratch_control - control structure
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* @control_flags: context information flags see &enum iwl_prph_scratch_flags
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* @reserved: reserved
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*/
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struct iwl_prph_scratch_control {
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__le32 control_flags;
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__le32 reserved;
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} __packed; /* PERIPH_SCRATCH_CONTROL_S */
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/*
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* struct iwl_prph_scratch_pnvm_cfg - PNVM scratch
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* @pnvm_base_addr: PNVM start address
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* @pnvm_size: the size of the PNVM image in bytes
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* @reserved: reserved
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*/
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struct iwl_prph_scratch_pnvm_cfg {
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__le64 pnvm_base_addr;
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__le32 pnvm_size;
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__le32 reserved;
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} __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */
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/**
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* struct iwl_prph_scrath_mem_desc_addr_array
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* @mem_descs: array of dram addresses.
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* Each address is the beggining of a pnvm payload.
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*/
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struct iwl_prph_scrath_mem_desc_addr_array {
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__le64 mem_descs[IPC_DRAM_MAP_ENTRY_NUM_MAX];
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} __packed; /* PERIPH_SCRATCH_MEM_DESC_ADDR_ARRAY_S_VER_1 */
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/*
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* struct iwl_prph_scratch_hwm_cfg - hwm config
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* @hwm_base_addr: hwm start address
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* @hwm_size: hwm size in DWs
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* @debug_token_config: debug preset
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*/
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struct iwl_prph_scratch_hwm_cfg {
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__le64 hwm_base_addr;
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__le32 hwm_size;
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__le32 debug_token_config;
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} __packed; /* PERIPH_SCRATCH_HWM_CFG_S */
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/*
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* struct iwl_prph_scratch_rbd_cfg - RBDs configuration
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* @free_rbd_addr: default queue free RB CB base address
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* @reserved: reserved
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*/
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struct iwl_prph_scratch_rbd_cfg {
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__le64 free_rbd_addr;
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__le32 reserved;
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} __packed; /* PERIPH_SCRATCH_RBD_CFG_S */
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/*
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* struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table
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* @base_addr: reduce power table address
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* @size: the size of the entire power table image
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*/
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struct iwl_prph_scratch_uefi_cfg {
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__le64 base_addr;
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__le32 size;
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__le32 reserved;
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} __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */
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/*
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* struct iwl_prph_scratch_step_cfg - prph scratch step configuration
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* @mbx_addr_0: [0:7] revision,
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* [8:15] cnvi_to_cnvr length,
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* [16:23] cnvr_to_cnvi channel length,
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* [24:31] radio1 reserved
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* @mbx_addr_1: [0:7] radio2 reserved
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*/
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struct iwl_prph_scratch_step_cfg {
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__le32 mbx_addr_0;
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__le32 mbx_addr_1;
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} __packed;
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/*
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* struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config
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* @version: version information of context info and HW
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* @control: control flags of FH configurations
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* @pnvm_cfg: ror configuration
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* @hwm_cfg: hwm configuration
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* @rbd_cfg: default RX queue configuration
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* @step_cfg: step configuration
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*/
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struct iwl_prph_scratch_ctrl_cfg {
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struct iwl_prph_scratch_version version;
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struct iwl_prph_scratch_control control;
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struct iwl_prph_scratch_pnvm_cfg pnvm_cfg;
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struct iwl_prph_scratch_hwm_cfg hwm_cfg;
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struct iwl_prph_scratch_rbd_cfg rbd_cfg;
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struct iwl_prph_scratch_uefi_cfg reduce_power_cfg;
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struct iwl_prph_scratch_step_cfg step_cfg;
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} __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */
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/*
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* struct iwl_prph_scratch - peripheral scratch mapping
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* @ctrl_cfg: control and configuration of prph scratch
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* @dram: firmware images addresses in DRAM
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* @reserved: reserved
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*/
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struct iwl_prph_scratch {
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struct iwl_prph_scratch_ctrl_cfg ctrl_cfg;
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__le32 reserved[10];
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struct iwl_context_info_dram dram;
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} __packed; /* PERIPH_SCRATCH_S */
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/*
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* struct iwl_prph_info - peripheral information
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* @boot_stage_mirror: reflects the value in the Boot Stage CSR register
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* @ipc_status_mirror: reflects the value in the IPC Status CSR register
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* @sleep_notif: indicates the peripheral sleep status
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* @reserved: reserved
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*/
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struct iwl_prph_info {
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__le32 boot_stage_mirror;
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__le32 ipc_status_mirror;
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__le32 sleep_notif;
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__le32 reserved;
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} __packed; /* PERIPH_INFO_S */
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/*
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* struct iwl_context_info_gen3 - device INIT configuration
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* @version: version of the context information
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* @size: size of context information in DWs
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* @config: context in which the peripheral would execute - a subset of
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* capability csr register published by the peripheral
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* @prph_info_base_addr: the peripheral information structure start address
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* @cr_head_idx_arr_base_addr: the completion ring head index array
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* start address
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* @tr_tail_idx_arr_base_addr: the transfer ring tail index array
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* start address
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* @cr_tail_idx_arr_base_addr: the completion ring tail index array
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* start address
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* @tr_head_idx_arr_base_addr: the transfer ring head index array
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* start address
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* @cr_idx_arr_size: number of entries in the completion ring index array
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* @tr_idx_arr_size: number of entries in the transfer ring index array
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* @mtr_base_addr: the message transfer ring start address
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* @mcr_base_addr: the message completion ring start address
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* @mtr_size: number of entries which the message transfer ring can hold
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* @mcr_size: number of entries which the message completion ring can hold
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* @mtr_doorbell_vec: the doorbell vector associated with the message
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* transfer ring
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* @mcr_doorbell_vec: the doorbell vector associated with the message
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* completion ring
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* @mtr_msi_vec: the MSI which shall be generated by the peripheral after
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* completing a transfer descriptor in the message transfer ring
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* @mcr_msi_vec: the MSI which shall be generated by the peripheral after
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* completing a completion descriptor in the message completion ring
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* @mtr_opt_header_size: the size of the optional header in the transfer
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* descriptor associated with the message transfer ring in DWs
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* @mtr_opt_footer_size: the size of the optional footer in the transfer
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* descriptor associated with the message transfer ring in DWs
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* @mcr_opt_header_size: the size of the optional header in the completion
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* descriptor associated with the message completion ring in DWs
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* @mcr_opt_footer_size: the size of the optional footer in the completion
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* descriptor associated with the message completion ring in DWs
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* @msg_rings_ctrl_flags: message rings control flags
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* @prph_info_msi_vec: the MSI which shall be generated by the peripheral
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* after updating the Peripheral Information structure
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* @prph_scratch_base_addr: the peripheral scratch structure start address
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* @prph_scratch_size: the size of the peripheral scratch structure in DWs
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* @reserved: reserved
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*/
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struct iwl_context_info_gen3 {
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__le16 version;
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__le16 size;
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__le32 config;
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__le64 prph_info_base_addr;
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__le64 cr_head_idx_arr_base_addr;
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__le64 tr_tail_idx_arr_base_addr;
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__le64 cr_tail_idx_arr_base_addr;
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__le64 tr_head_idx_arr_base_addr;
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__le16 cr_idx_arr_size;
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__le16 tr_idx_arr_size;
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__le64 mtr_base_addr;
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__le64 mcr_base_addr;
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__le16 mtr_size;
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__le16 mcr_size;
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__le16 mtr_doorbell_vec;
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__le16 mcr_doorbell_vec;
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__le16 mtr_msi_vec;
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__le16 mcr_msi_vec;
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u8 mtr_opt_header_size;
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u8 mtr_opt_footer_size;
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u8 mcr_opt_header_size;
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u8 mcr_opt_footer_size;
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__le16 msg_rings_ctrl_flags;
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__le16 prph_info_msi_vec;
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__le64 prph_scratch_base_addr;
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__le32 prph_scratch_size;
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__le32 reserved;
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} __packed; /* IPC_CONTEXT_INFO_S */
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int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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const struct fw_img *fw);
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void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive);
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int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans,
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const struct iwl_pnvm_image *pnvm_payloads,
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const struct iwl_ucode_capabilities *capa);
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void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
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const struct iwl_ucode_capabilities *capa);
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int
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iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans,
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const struct iwl_pnvm_image *payloads,
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const struct iwl_ucode_capabilities *capa);
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void
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iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
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const struct iwl_ucode_capabilities *capa);
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int iwl_trans_pcie_ctx_info_gen3_set_step(struct iwl_trans *trans,
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u32 mbx_addr_0_step, u32 mbx_addr_1_step);
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#endif /* __iwl_context_info_file_gen3_h__ */
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