531 lines
13 KiB
C
531 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2003-2014, 2018-2022 Intel Corporation
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* Copyright (C) 2015-2016 Intel Deutschland GmbH
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/export.h>
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#include "iwl-drv.h"
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#include "iwl-io.h"
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#include "iwl-csr.h"
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#include "iwl-debug.h"
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#include "iwl-prph.h"
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#include "iwl-fh.h"
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void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val)
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{
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trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val);
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iwl_trans_write8(trans, ofs, val);
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}
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IWL_EXPORT_SYMBOL(iwl_write8);
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void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val)
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{
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trace_iwlwifi_dev_iowrite32(trans->dev, ofs, val);
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iwl_trans_write32(trans, ofs, val);
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}
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IWL_EXPORT_SYMBOL(iwl_write32);
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void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val)
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{
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trace_iwlwifi_dev_iowrite64(trans->dev, ofs, val);
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iwl_trans_write32(trans, ofs, lower_32_bits(val));
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iwl_trans_write32(trans, ofs + 4, upper_32_bits(val));
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}
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IWL_EXPORT_SYMBOL(iwl_write64);
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u32 iwl_read32(struct iwl_trans *trans, u32 ofs)
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{
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u32 val = iwl_trans_read32(trans, ofs);
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trace_iwlwifi_dev_ioread32(trans->dev, ofs, val);
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return val;
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}
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IWL_EXPORT_SYMBOL(iwl_read32);
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#define IWL_POLL_INTERVAL 10 /* microseconds */
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int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout)
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{
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int t = 0;
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do {
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if ((iwl_read32(trans, addr) & mask) == (bits & mask))
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return t;
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udelay(IWL_POLL_INTERVAL);
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t += IWL_POLL_INTERVAL;
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} while (t < timeout);
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return -ETIMEDOUT;
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}
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IWL_EXPORT_SYMBOL(iwl_poll_bit);
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u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
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{
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if (iwl_trans_grab_nic_access(trans)) {
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u32 value = iwl_read32(trans, reg);
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iwl_trans_release_nic_access(trans);
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return value;
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}
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/* return as if we have a HW timeout/failure */
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return 0x5a5a5a5a;
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}
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IWL_EXPORT_SYMBOL(iwl_read_direct32);
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void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
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{
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if (iwl_trans_grab_nic_access(trans)) {
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iwl_write32(trans, reg, value);
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iwl_trans_release_nic_access(trans);
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}
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}
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IWL_EXPORT_SYMBOL(iwl_write_direct32);
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void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value)
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{
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if (iwl_trans_grab_nic_access(trans)) {
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iwl_write64(trans, reg, value);
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iwl_trans_release_nic_access(trans);
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}
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}
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IWL_EXPORT_SYMBOL(iwl_write_direct64);
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int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
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int timeout)
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{
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int t = 0;
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do {
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if ((iwl_read_direct32(trans, addr) & mask) == mask)
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return t;
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udelay(IWL_POLL_INTERVAL);
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t += IWL_POLL_INTERVAL;
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} while (t < timeout);
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return -ETIMEDOUT;
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}
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IWL_EXPORT_SYMBOL(iwl_poll_direct_bit);
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u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs)
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{
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u32 val = iwl_trans_read_prph(trans, ofs);
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trace_iwlwifi_dev_ioread_prph32(trans->dev, ofs, val);
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return val;
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}
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IWL_EXPORT_SYMBOL(iwl_read_prph_no_grab);
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void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val)
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{
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trace_iwlwifi_dev_iowrite_prph32(trans->dev, ofs, val);
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iwl_trans_write_prph(trans, ofs, val);
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}
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IWL_EXPORT_SYMBOL(iwl_write_prph_no_grab);
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void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val)
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{
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trace_iwlwifi_dev_iowrite_prph64(trans->dev, ofs, val);
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iwl_write_prph_no_grab(trans, ofs, val & 0xffffffff);
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iwl_write_prph_no_grab(trans, ofs + 4, val >> 32);
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}
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IWL_EXPORT_SYMBOL(iwl_write_prph64_no_grab);
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u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
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{
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if (iwl_trans_grab_nic_access(trans)) {
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u32 val = iwl_read_prph_no_grab(trans, ofs);
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iwl_trans_release_nic_access(trans);
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return val;
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}
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/* return as if we have a HW timeout/failure */
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return 0x5a5a5a5a;
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}
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IWL_EXPORT_SYMBOL(iwl_read_prph);
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void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs, u32 val, u32 delay_ms)
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{
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if (iwl_trans_grab_nic_access(trans)) {
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mdelay(delay_ms);
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iwl_write_prph_no_grab(trans, ofs, val);
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iwl_trans_release_nic_access(trans);
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}
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}
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IWL_EXPORT_SYMBOL(iwl_write_prph_delay);
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int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout)
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{
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int t = 0;
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do {
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if ((iwl_read_prph(trans, addr) & mask) == (bits & mask))
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return t;
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udelay(IWL_POLL_INTERVAL);
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t += IWL_POLL_INTERVAL;
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} while (t < timeout);
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return -ETIMEDOUT;
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}
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void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
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{
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if (iwl_trans_grab_nic_access(trans)) {
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iwl_write_prph_no_grab(trans, ofs,
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iwl_read_prph_no_grab(trans, ofs) |
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mask);
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iwl_trans_release_nic_access(trans);
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}
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}
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IWL_EXPORT_SYMBOL(iwl_set_bits_prph);
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void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
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u32 bits, u32 mask)
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{
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if (iwl_trans_grab_nic_access(trans)) {
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iwl_write_prph_no_grab(trans, ofs,
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(iwl_read_prph_no_grab(trans, ofs) &
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mask) | bits);
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iwl_trans_release_nic_access(trans);
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}
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}
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IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph);
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void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
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{
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u32 val;
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if (iwl_trans_grab_nic_access(trans)) {
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val = iwl_read_prph_no_grab(trans, ofs);
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iwl_write_prph_no_grab(trans, ofs, (val & ~mask));
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iwl_trans_release_nic_access(trans);
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}
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}
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IWL_EXPORT_SYMBOL(iwl_clear_bits_prph);
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void iwl_force_nmi(struct iwl_trans *trans)
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{
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if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_9000)
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iwl_write_prph_delay(trans, DEVICE_SET_NMI_REG,
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DEVICE_SET_NMI_VAL_DRV, 1);
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else if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
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iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
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UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER);
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else if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ)
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iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
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UREG_DOORBELL_TO_ISR6_NMI_BIT);
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else
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iwl_write32(trans, CSR_DOORBELL_VECTOR,
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UREG_DOORBELL_TO_ISR6_NMI_BIT);
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}
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IWL_EXPORT_SYMBOL(iwl_force_nmi);
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static const char *get_rfh_string(int cmd)
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{
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#define IWL_CMD(x) case x: return #x
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#define IWL_CMD_MQ(arg, reg, q) { if (arg == reg(q)) return #reg; }
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int i;
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for (i = 0; i < IWL_MAX_RX_HW_QUEUES; i++) {
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IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_BA_LSB, i);
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IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_WIDX, i);
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IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_RIDX, i);
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IWL_CMD_MQ(cmd, RFH_Q_URBD_STTS_WPTR_LSB, i);
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}
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switch (cmd) {
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IWL_CMD(RFH_RXF_DMA_CFG);
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IWL_CMD(RFH_GEN_CFG);
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IWL_CMD(RFH_GEN_STATUS);
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IWL_CMD(FH_TSSR_TX_STATUS_REG);
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IWL_CMD(FH_TSSR_TX_ERROR_REG);
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default:
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return "UNKNOWN";
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}
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#undef IWL_CMD_MQ
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}
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struct reg {
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u32 addr;
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bool is64;
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};
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static int iwl_dump_rfh(struct iwl_trans *trans, char **buf)
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{
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int i, q;
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int num_q = trans->num_rx_queues;
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static const u32 rfh_tbl[] = {
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RFH_RXF_DMA_CFG,
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RFH_GEN_CFG,
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RFH_GEN_STATUS,
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FH_TSSR_TX_STATUS_REG,
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FH_TSSR_TX_ERROR_REG,
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};
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static const struct reg rfh_mq_tbl[] = {
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{ RFH_Q0_FRBDCB_BA_LSB, true },
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{ RFH_Q0_FRBDCB_WIDX, false },
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{ RFH_Q0_FRBDCB_RIDX, false },
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{ RFH_Q0_URBD_STTS_WPTR_LSB, true },
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};
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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if (buf) {
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int pos = 0;
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/*
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* Register (up to 34 for name + 8 blank/q for MQ): 40 chars
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* Colon + space: 2 characters
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* 0X%08x: 10 characters
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* New line: 1 character
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* Total of 53 characters
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*/
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size_t bufsz = ARRAY_SIZE(rfh_tbl) * 53 +
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ARRAY_SIZE(rfh_mq_tbl) * 53 * num_q + 40;
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*buf = kmalloc(bufsz, GFP_KERNEL);
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if (!*buf)
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return -ENOMEM;
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pos += scnprintf(*buf + pos, bufsz - pos,
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"RFH register values:\n");
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for (i = 0; i < ARRAY_SIZE(rfh_tbl); i++)
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pos += scnprintf(*buf + pos, bufsz - pos,
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"%40s: 0X%08x\n",
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get_rfh_string(rfh_tbl[i]),
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iwl_read_prph(trans, rfh_tbl[i]));
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for (i = 0; i < ARRAY_SIZE(rfh_mq_tbl); i++)
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for (q = 0; q < num_q; q++) {
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u32 addr = rfh_mq_tbl[i].addr;
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addr += q * (rfh_mq_tbl[i].is64 ? 8 : 4);
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pos += scnprintf(*buf + pos, bufsz - pos,
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"%34s(q %2d): 0X%08x\n",
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get_rfh_string(addr), q,
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iwl_read_prph(trans, addr));
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}
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return pos;
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}
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#endif
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IWL_ERR(trans, "RFH register values:\n");
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for (i = 0; i < ARRAY_SIZE(rfh_tbl); i++)
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IWL_ERR(trans, " %34s: 0X%08x\n",
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get_rfh_string(rfh_tbl[i]),
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iwl_read_prph(trans, rfh_tbl[i]));
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for (i = 0; i < ARRAY_SIZE(rfh_mq_tbl); i++)
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for (q = 0; q < num_q; q++) {
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u32 addr = rfh_mq_tbl[i].addr;
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addr += q * (rfh_mq_tbl[i].is64 ? 8 : 4);
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IWL_ERR(trans, " %34s(q %d): 0X%08x\n",
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get_rfh_string(addr), q,
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iwl_read_prph(trans, addr));
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}
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return 0;
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}
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static const char *get_fh_string(int cmd)
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{
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switch (cmd) {
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IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
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IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
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IWL_CMD(FH_RSCSR_CHNL0_WPTR);
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IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
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IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
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IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
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IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
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IWL_CMD(FH_TSSR_TX_STATUS_REG);
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IWL_CMD(FH_TSSR_TX_ERROR_REG);
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default:
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return "UNKNOWN";
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}
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#undef IWL_CMD
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}
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int iwl_dump_fh(struct iwl_trans *trans, char **buf)
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{
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int i;
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static const u32 fh_tbl[] = {
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FH_RSCSR_CHNL0_STTS_WPTR_REG,
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FH_RSCSR_CHNL0_RBDCB_BASE_REG,
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FH_RSCSR_CHNL0_WPTR,
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FH_MEM_RCSR_CHNL0_CONFIG_REG,
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FH_MEM_RSSR_SHARED_CTRL_REG,
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FH_MEM_RSSR_RX_STATUS_REG,
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FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
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FH_TSSR_TX_STATUS_REG,
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FH_TSSR_TX_ERROR_REG
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};
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if (trans->trans_cfg->mq_rx_supported)
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return iwl_dump_rfh(trans, buf);
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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if (buf) {
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int pos = 0;
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size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
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*buf = kmalloc(bufsz, GFP_KERNEL);
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if (!*buf)
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return -ENOMEM;
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pos += scnprintf(*buf + pos, bufsz - pos,
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"FH register values:\n");
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for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
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pos += scnprintf(*buf + pos, bufsz - pos,
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" %34s: 0X%08x\n",
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get_fh_string(fh_tbl[i]),
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iwl_read_direct32(trans, fh_tbl[i]));
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return pos;
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}
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#endif
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IWL_ERR(trans, "FH register values:\n");
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for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
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IWL_ERR(trans, " %34s: 0X%08x\n",
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get_fh_string(fh_tbl[i]),
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iwl_read_direct32(trans, fh_tbl[i]));
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return 0;
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}
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#define IWL_HOST_MON_BLOCK_PEMON 0x00
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#define IWL_HOST_MON_BLOCK_HIPM 0x22
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#define IWL_HOST_MON_BLOCK_PEMON_VEC0 0x00
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#define IWL_HOST_MON_BLOCK_PEMON_VEC1 0x01
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#define IWL_HOST_MON_BLOCK_PEMON_WFPM 0x06
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static void iwl_dump_host_monitor_block(struct iwl_trans *trans,
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u32 block, u32 vec, u32 iter)
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{
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int i;
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IWL_ERR(trans, "Host monitor block 0x%x vector 0x%x\n", block, vec);
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iwl_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) | vec);
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for (i = 0; i < iter; i++)
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IWL_ERR(trans, " value [iter %d]: 0x%08x\n",
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i, iwl_read32(trans, CSR_MONITOR_STATUS_REG));
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}
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static void iwl_dump_host_monitor(struct iwl_trans *trans)
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{
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switch (trans->trans_cfg->device_family) {
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case IWL_DEVICE_FAMILY_22000:
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case IWL_DEVICE_FAMILY_AX210:
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IWL_ERR(trans, "CSR_RESET = 0x%x\n",
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iwl_read32(trans, CSR_RESET));
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iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
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IWL_HOST_MON_BLOCK_PEMON_VEC0, 15);
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iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
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IWL_HOST_MON_BLOCK_PEMON_VEC1, 15);
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iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
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IWL_HOST_MON_BLOCK_PEMON_WFPM, 15);
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iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_HIPM,
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IWL_HOST_MON_BLOCK_PEMON_VEC0, 1);
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break;
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default:
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/* not supported yet */
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return;
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}
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}
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int iwl_finish_nic_init(struct iwl_trans *trans)
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{
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const struct iwl_cfg_trans_params *cfg_trans = trans->trans_cfg;
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u32 poll_ready;
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int err;
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if (cfg_trans->bisr_workaround) {
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/* ensure the TOP FSM isn't still in previous reset */
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mdelay(2);
|
|
}
|
|
|
|
/*
|
|
* Set "initialization complete" bit to move adapter from
|
|
* D0U* --> D0A* (powered-up active) state.
|
|
*/
|
|
if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_BZ) {
|
|
iwl_set_bit(trans, CSR_GP_CNTRL,
|
|
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
|
|
CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
|
|
poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
|
|
} else {
|
|
iwl_set_bit(trans, CSR_GP_CNTRL,
|
|
CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
|
|
poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY;
|
|
}
|
|
|
|
if (cfg_trans->device_family == IWL_DEVICE_FAMILY_8000)
|
|
udelay(2);
|
|
|
|
/*
|
|
* Wait for clock stabilization; once stabilized, access to
|
|
* device-internal resources is supported, e.g. iwl_write_prph()
|
|
* and accesses to uCode SRAM.
|
|
*/
|
|
err = iwl_poll_bit(trans, CSR_GP_CNTRL, poll_ready, poll_ready, 25000);
|
|
if (err < 0) {
|
|
IWL_DEBUG_INFO(trans, "Failed to wake NIC\n");
|
|
|
|
iwl_dump_host_monitor(trans);
|
|
}
|
|
|
|
if (cfg_trans->bisr_workaround) {
|
|
/* ensure BISR shift has finished */
|
|
udelay(200);
|
|
}
|
|
|
|
return err < 0 ? err : 0;
|
|
}
|
|
IWL_EXPORT_SYMBOL(iwl_finish_nic_init);
|
|
|
|
void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr,
|
|
u32 sw_err_bit)
|
|
{
|
|
unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
|
|
bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
|
|
|
|
/* if the interrupts were already disabled, there is no point in
|
|
* calling iwl_disable_interrupts
|
|
*/
|
|
if (interrupts_enabled)
|
|
iwl_trans_interrupts(trans, false);
|
|
|
|
iwl_force_nmi(trans);
|
|
while (time_after(timeout, jiffies)) {
|
|
u32 inta_hw = iwl_read32(trans, inta_addr);
|
|
|
|
/* Error detected by uCode */
|
|
if (inta_hw & sw_err_bit) {
|
|
/* Clear causes register */
|
|
iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
|
|
break;
|
|
}
|
|
|
|
mdelay(1);
|
|
}
|
|
|
|
/* enable interrupts only if there were already enabled before this
|
|
* function to avoid a case were the driver enable interrupts before
|
|
* proper configurations were made
|
|
*/
|
|
if (interrupts_enabled)
|
|
iwl_trans_interrupts(trans, true);
|
|
|
|
iwl_trans_fw_error(trans, false);
|
|
}
|