535 lines
15 KiB
C
535 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2017 Intel Deutschland GmbH
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* Copyright (C) 2018-2023 Intel Corporation
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*/
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#include "iwl-trans.h"
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#include "iwl-prph.h"
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#include "iwl-context-info.h"
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#include "iwl-context-info-gen3.h"
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#include "internal.h"
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#include "fw/dbg.h"
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#define FW_RESET_TIMEOUT (HZ / 5)
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/*
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* Start up NIC's basic functionality after it has been reset
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* (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
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* NOTE: This does not load uCode nor start the embedded processor
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*/
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int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
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{
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int ret = 0;
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IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
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/*
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* Use "set_bit" below rather than "write", to preserve any hardware
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* bits already set by default after reset.
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*/
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/*
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* Disable L0s without affecting L1;
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* don't wait for ICH L0s (ICH bug W/A)
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*/
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iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
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/* Set FH wait threshold to maximum (HW error during stress W/A) */
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iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
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/*
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* Enable HAP INTA (interrupt from management bus) to
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* wake device's PCI Express link L1a -> L0s
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*/
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iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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iwl_pcie_apm_config(trans);
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ret = iwl_finish_nic_init(trans);
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if (ret)
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return ret;
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set_bit(STATUS_DEVICE_ENABLED, &trans->status);
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return 0;
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}
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static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
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{
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IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
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if (op_mode_leave) {
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if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
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iwl_pcie_gen2_apm_init(trans);
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/* inform ME that we are leaving */
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iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
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CSR_RESET_LINK_PWR_MGMT_DISABLED);
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iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_PREPARE |
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CSR_HW_IF_CONFIG_REG_ENABLE_PME);
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mdelay(1);
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iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
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CSR_RESET_LINK_PWR_MGMT_DISABLED);
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mdelay(5);
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}
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clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
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/* Stop device's DMA activity */
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iwl_pcie_apm_stop_master(trans);
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iwl_trans_sw_reset(trans, false);
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/*
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* Clear "initialization complete" bit to move adapter from
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* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
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*/
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if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
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else
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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}
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static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int ret;
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trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
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if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
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iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
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UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
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else if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
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iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
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UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
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else
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iwl_write32(trans, CSR_DOORBELL_VECTOR,
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UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
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/* wait 200ms */
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ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
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trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
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FW_RESET_TIMEOUT);
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if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
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u32 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
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IWL_ERR(trans,
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"timeout waiting for FW reset ACK (inta_hw=0x%x)\n",
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inta_hw);
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if (!(inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE))
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iwl_trans_fw_error(trans, true);
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}
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trans_pcie->fw_reset_state = FW_RESET_IDLE;
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}
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void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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lockdep_assert_held(&trans_pcie->mutex);
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if (trans_pcie->is_down)
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return;
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if (trans->state >= IWL_TRANS_FW_STARTED)
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if (trans_pcie->fw_reset_handshake)
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iwl_trans_pcie_fw_reset_handshake(trans);
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trans_pcie->is_down = true;
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/* tell the device to stop sending interrupts */
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iwl_disable_interrupts(trans);
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/* device going down, Stop using ICT table */
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iwl_pcie_disable_ict(trans);
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/*
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* If a HW restart happens during firmware loading,
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* then the firmware loading might call this function
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* and later it might be called again due to the
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* restart. So don't process again if the device is
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* already dead.
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*/
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if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
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IWL_DEBUG_INFO(trans,
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"DEVICE_ENABLED bit was set and is now cleared\n");
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iwl_pcie_rx_napi_sync(trans);
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iwl_txq_gen2_tx_free(trans);
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iwl_pcie_rx_stop(trans);
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}
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iwl_pcie_ctxt_info_free_paging(trans);
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if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
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iwl_pcie_ctxt_info_gen3_free(trans, false);
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else
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iwl_pcie_ctxt_info_free(trans);
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/* Stop the device, and put it in low power state */
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iwl_pcie_gen2_apm_stop(trans, false);
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/* re-take ownership to prevent other users from stealing the device */
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iwl_trans_sw_reset(trans, true);
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/*
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* Upon stop, the IVAR table gets erased, so msi-x won't
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* work. This causes a bug in RF-KILL flows, since the interrupt
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* that enables radio won't fire on the correct irq, and the
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* driver won't be able to handle the interrupt.
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* Configure the IVAR table again after reset.
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*/
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iwl_pcie_conf_msix_hw(trans_pcie);
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/*
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* Upon stop, the APM issues an interrupt if HW RF kill is set.
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* This is a bug in certain verions of the hardware.
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* Certain devices also keep sending HW RF kill interrupt all
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* the time, unless the interrupt is ACKed even if the interrupt
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* should be masked. Re-ACK all the interrupts here.
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*/
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iwl_disable_interrupts(trans);
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/* clear all status bits */
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clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
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clear_bit(STATUS_INT_ENABLED, &trans->status);
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clear_bit(STATUS_TPOWER_PMI, &trans->status);
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/*
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* Even if we stop the HW, we still want the RF kill
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* interrupt
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*/
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iwl_enable_rfkill_int(trans);
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}
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void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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bool was_in_rfkill;
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iwl_op_mode_time_point(trans->op_mode,
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IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
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NULL);
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mutex_lock(&trans_pcie->mutex);
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trans_pcie->opmode_down = true;
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was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
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_iwl_trans_pcie_gen2_stop_device(trans);
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iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
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mutex_unlock(&trans_pcie->mutex);
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}
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static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
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trans->cfg->min_txq_size);
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/* TODO: most of the logic can be removed in A0 - but not in Z0 */
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spin_lock_bh(&trans_pcie->irq_lock);
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iwl_pcie_gen2_apm_init(trans);
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spin_unlock_bh(&trans_pcie->irq_lock);
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iwl_op_mode_nic_config(trans->op_mode);
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/* Allocate the RX queue, or reset if it is already allocated */
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if (iwl_pcie_gen2_rx_init(trans))
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return -ENOMEM;
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/* Allocate or reset and init all Tx and Command queues */
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if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size))
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return -ENOMEM;
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/* enable shadow regs in HW */
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iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
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IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
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return 0;
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}
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static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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char *buf = trans_pcie->rf_name;
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size_t buflen = sizeof(trans_pcie->rf_name);
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size_t pos;
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u32 version;
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if (buf[0])
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return;
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switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
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case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
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pos = scnprintf(buf, buflen, "JF");
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break;
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case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
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pos = scnprintf(buf, buflen, "GF");
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break;
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case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
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pos = scnprintf(buf, buflen, "GF4");
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break;
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case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
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pos = scnprintf(buf, buflen, "HR");
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break;
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case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
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pos = scnprintf(buf, buflen, "HR1");
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break;
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case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
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pos = scnprintf(buf, buflen, "HRCDB");
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break;
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case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_MS):
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pos = scnprintf(buf, buflen, "MS");
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break;
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default:
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return;
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}
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switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
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case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
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case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
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case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
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version = iwl_read_prph(trans, CNVI_MBOX_C);
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switch (version) {
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case 0x20000:
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pos += scnprintf(buf + pos, buflen - pos, " B3");
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break;
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case 0x120000:
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pos += scnprintf(buf + pos, buflen - pos, " B5");
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break;
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default:
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pos += scnprintf(buf + pos, buflen - pos,
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" (0x%x)", version);
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break;
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}
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break;
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default:
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break;
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}
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pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
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trans->hw_rf_id);
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IWL_INFO(trans, "Detected RF %s\n", buf);
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/*
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* also add a \n for debugfs - need to do it after printing
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* since our IWL_INFO machinery wants to see a static \n at
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* the end of the string
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*/
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pos += scnprintf(buf + pos, buflen - pos, "\n");
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}
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void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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iwl_pcie_reset_ict(trans);
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/* make sure all queue are not stopped/used */
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memset(trans->txqs.queue_stopped, 0,
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sizeof(trans->txqs.queue_stopped));
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memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
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/* now that we got alive we can free the fw image & the context info.
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* paging memory cannot be freed included since FW will still use it
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*/
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if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
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iwl_pcie_ctxt_info_gen3_free(trans, true);
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else
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iwl_pcie_ctxt_info_free(trans);
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/*
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* Re-enable all the interrupts, including the RF-Kill one, now that
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* the firmware is alive.
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*/
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iwl_enable_interrupts(trans);
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mutex_lock(&trans_pcie->mutex);
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iwl_pcie_check_hw_rf_kill(trans);
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iwl_pcie_get_rf_name(trans);
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mutex_unlock(&trans_pcie->mutex);
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}
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static bool iwl_pcie_set_ltr(struct iwl_trans *trans)
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{
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u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
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u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
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CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
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u32_encode_bits(250,
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CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
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CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
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u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
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CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
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u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
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/*
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* To workaround hardware latency issues during the boot process,
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* initialize the LTR to ~250 usec (see ltr_val above).
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* The firmware initializes this again later (to a smaller value).
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*/
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if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
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trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
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!trans->trans_cfg->integrated) {
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iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
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return true;
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}
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if (trans->trans_cfg->integrated &&
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trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
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iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
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iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
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return true;
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}
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if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
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/* First clear the interrupt, just in case */
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iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
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MSIX_HW_INT_CAUSES_REG_IML);
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/* In this case, unfortunately the same ROM bug exists in the
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* device (not setting LTR correctly), but we don't have control
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* over the settings from the host due to some hardware security
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* features. The only workaround we've been able to come up with
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* so far is to try to keep the CPU and device busy by polling
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* it and the IML (image loader) completed interrupt.
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*/
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return false;
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}
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/* nothing needs to be done on other devices */
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return true;
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}
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static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)
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{
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/* in practice, this seems to complete in around 20-30ms at most, wait 100 */
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#define IML_WAIT_TIMEOUT (HZ / 10)
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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unsigned long end_time = jiffies + IML_WAIT_TIMEOUT;
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u32 value, loops = 0;
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bool irq = false;
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if (WARN_ON(!trans_pcie->iml))
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return;
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value = iwl_read32(trans, CSR_LTR_LAST_MSG);
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IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",
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value);
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while (time_before(jiffies, end_time)) {
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if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
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MSIX_HW_INT_CAUSES_REG_IML) {
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irq = true;
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break;
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}
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/* Keep the CPU and device busy. */
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value = iwl_read32(trans, CSR_LTR_LAST_MSG);
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loops++;
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}
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IWL_DEBUG_INFO(trans,
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"Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n",
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irq, loops, value);
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/* We don't fail here even if we timed out - maybe we get lucky and the
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* interrupt comes in later (and we get alive from firmware) and then
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* we're all happy - but if not we'll fail on alive timeout or get some
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* other error out.
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*/
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}
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int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
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const struct fw_img *fw, bool run_in_rfkill)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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bool hw_rfkill, keep_ram_busy;
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int ret;
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/* This may fail if AMT took ownership of the device */
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if (iwl_pcie_prepare_card_hw(trans)) {
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IWL_WARN(trans, "Exit HW not ready\n");
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return -EIO;
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}
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iwl_enable_rfkill_int(trans);
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iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
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/*
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* We enabled the RF-Kill interrupt and the handler may very
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* well be running. Disable the interrupts to make sure no other
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* interrupt can be fired.
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*/
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iwl_disable_interrupts(trans);
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/* Make sure it finished running */
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iwl_pcie_synchronize_irqs(trans);
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mutex_lock(&trans_pcie->mutex);
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/* If platform's RF_KILL switch is NOT set to KILL */
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hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
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if (hw_rfkill && !run_in_rfkill) {
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ret = -ERFKILL;
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goto out;
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}
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/* Someone called stop_device, don't try to start_fw */
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if (trans_pcie->is_down) {
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IWL_WARN(trans,
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"Can't start_fw since the HW hasn't been started\n");
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ret = -EIO;
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goto out;
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}
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/* make sure rfkill handshake bits are cleared */
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iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
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iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
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CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
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/* clear (again), then enable host interrupts */
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iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
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ret = iwl_pcie_gen2_nic_init(trans);
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if (ret) {
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IWL_ERR(trans, "Unable to init nic\n");
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goto out;
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}
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if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
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ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
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else
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ret = iwl_pcie_ctxt_info_init(trans, fw);
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if (ret)
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goto out;
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keep_ram_busy = !iwl_pcie_set_ltr(trans);
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if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
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iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
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iwl_set_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_ROM_START);
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} else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
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iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
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} else {
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iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
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}
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if (keep_ram_busy)
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iwl_pcie_spin_for_iml(trans);
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/* re-check RF-Kill state since we may have missed the interrupt */
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hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
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if (hw_rfkill && !run_in_rfkill)
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ret = -ERFKILL;
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out:
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mutex_unlock(&trans_pcie->mutex);
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return ret;
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}
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