411 lines
12 KiB
C
411 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/* Copyright(c) 2018-2019 Realtek Corporation.
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*/
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#include "main.h"
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#include "reg.h"
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#include "bf.h"
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#include "debug.h"
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void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
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struct ieee80211_bss_conf *bss_conf)
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{
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struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
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struct rtw_bfee *bfee = &rtwvif->bfee;
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struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
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if (bfee->role == RTW_BFEE_NONE)
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return;
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if (bfee->role == RTW_BFEE_MU)
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bfinfo->bfer_mu_cnt--;
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else if (bfee->role == RTW_BFEE_SU)
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bfinfo->bfer_su_cnt--;
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rtw_chip_config_bfee(rtwdev, rtwvif, bfee, false);
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bfee->role = RTW_BFEE_NONE;
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}
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void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
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struct ieee80211_bss_conf *bss_conf)
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{
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const struct rtw_chip_info *chip = rtwdev->chip;
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struct ieee80211_hw *hw = rtwdev->hw;
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struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
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struct rtw_bfee *bfee = &rtwvif->bfee;
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struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
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struct ieee80211_sta *sta;
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struct ieee80211_sta_vht_cap *vht_cap;
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struct ieee80211_sta_vht_cap *ic_vht_cap;
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const u8 *bssid = bss_conf->bssid;
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u32 sound_dim;
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u8 i;
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if (!(chip->band & RTW_BAND_5G))
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return;
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rcu_read_lock();
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sta = ieee80211_find_sta(vif, bssid);
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if (!sta) {
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rcu_read_unlock();
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rtw_warn(rtwdev, "failed to find station entry for bss %pM\n",
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bssid);
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return;
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}
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ic_vht_cap = &hw->wiphy->bands[NL80211_BAND_5GHZ]->vht_cap;
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vht_cap = &sta->deflink.vht_cap;
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rcu_read_unlock();
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if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) &&
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(vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE)) {
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if (bfinfo->bfer_mu_cnt >= chip->bfer_mu_max_num) {
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rtw_dbg(rtwdev, RTW_DBG_BF, "mu bfer number over limit\n");
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return;
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}
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ether_addr_copy(bfee->mac_addr, bssid);
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bfee->role = RTW_BFEE_MU;
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bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
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bfee->aid = vif->cfg.aid;
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bfinfo->bfer_mu_cnt++;
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rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
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} else if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE) &&
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(vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
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if (bfinfo->bfer_su_cnt >= chip->bfer_su_max_num) {
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rtw_dbg(rtwdev, RTW_DBG_BF, "su bfer number over limit\n");
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return;
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}
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sound_dim = vht_cap->cap &
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IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK;
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sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT;
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ether_addr_copy(bfee->mac_addr, bssid);
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bfee->role = RTW_BFEE_SU;
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bfee->sound_dim = (u8)sound_dim;
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bfee->g_id = 0;
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bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
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bfinfo->bfer_su_cnt++;
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for (i = 0; i < chip->bfer_su_max_num; i++) {
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if (!test_bit(i, bfinfo->bfer_su_reg_maping)) {
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set_bit(i, bfinfo->bfer_su_reg_maping);
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bfee->su_reg_index = i;
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break;
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}
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}
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rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
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}
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}
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void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev,
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struct mu_bfer_init_para *param)
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{
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u16 mu_bf_ctl = 0;
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u8 *addr = param->bfer_address;
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int i;
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for (i = 0; i < ETH_ALEN; i++)
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rtw_write8(rtwdev, REG_ASSOCIATED_BFMER0_INFO + i, addr[i]);
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rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
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rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
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mu_bf_ctl = rtw_read16(rtwdev, REG_WMAC_MU_BF_CTL) & 0xC000;
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mu_bf_ctl |= param->my_aid | (param->csi_length_sel << 12);
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rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, mu_bf_ctl);
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}
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void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
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enum rtw_trx_desc_rate rate)
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{
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u32 psf_ctl = 0;
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u8 csi_rsc = 0x1;
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psf_ctl = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
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BIT_WMAC_USE_NDPARATE |
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(csi_rsc << 13);
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rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
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RTW_SND_CTRL_SOUNDING);
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rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, 0x26);
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rtw_write8_clr(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF_REPORT_POLL);
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rtw_write8_clr(rtwdev, REG_RXFLTMAP4, BIT_RXFLTMAP4_BF_REPORT_POLL);
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if (vif->net_type == RTW_NET_AP_MODE)
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rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl | BIT(12));
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else
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rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl & ~BIT(12));
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}
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void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param)
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{
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u8 mu_tbl_sel;
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u8 mu_valid;
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mu_valid = rtw_read8(rtwdev, REG_MU_TX_CTL) &
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~BIT_MASK_R_MU_TABLE_VALID;
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rtw_write8(rtwdev, REG_MU_TX_CTL,
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(mu_valid | BIT(0) | BIT(1)) & ~(BIT(7)));
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mu_tbl_sel = rtw_read8(rtwdev, REG_MU_TX_CTL + 1) & 0xF8;
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rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel);
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rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[0]);
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rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);
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rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
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param->given_user_pos[1]);
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rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel | 1);
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rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[1]);
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rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);
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rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
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param->given_user_pos[3]);
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}
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void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev)
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{
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rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
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rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
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rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
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rtw_write8(rtwdev, REG_MU_TX_CTL, 0);
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}
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void rtw_bf_del_sounding(struct rtw_dev *rtwdev)
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{
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rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 0);
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}
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void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif,
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struct rtw_bfee *bfee)
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{
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u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
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u8 nr_index = bfee->sound_dim;
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u8 grouping = 0, codebookinfo = 1, coefficientsize = 3;
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u32 addr_bfer_info, addr_csi_rpt, csi_param;
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u8 i;
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rtw_dbg(rtwdev, RTW_DBG_BF, "config as an su bfee\n");
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switch (bfee->su_reg_index) {
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case 1:
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addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO;
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addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20 + 2;
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break;
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case 0:
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default:
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addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO;
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addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20;
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break;
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}
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/* Sounding protocol control */
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rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
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RTW_SND_CTRL_SOUNDING);
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/* MAC address/Partial AID of Beamformer */
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for (i = 0; i < ETH_ALEN; i++)
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rtw_write8(rtwdev, addr_bfer_info + i, bfee->mac_addr[i]);
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csi_param = (u16)((coefficientsize << 10) |
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(codebookinfo << 8) |
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(grouping << 6) |
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(nr_index << 3) |
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nc_index);
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rtw_write16(rtwdev, addr_csi_rpt, csi_param);
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/* ndp rx standby timer */
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rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, RTW_NDP_RX_STANDBY_TIME);
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}
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EXPORT_SYMBOL(rtw_bf_enable_bfee_su);
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/* nc index: 1 2T2R 0 1T1R
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* nr index: 1 use Nsts 0 use reg setting
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* codebookinfo: 1 802.11ac 3 802.11n
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*/
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void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif,
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struct rtw_bfee *bfee)
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{
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struct rtw_bf_info *bf_info = &rtwdev->bf_info;
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struct mu_bfer_init_para param;
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u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
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u8 nr_index = 1;
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u8 grouping = 0, codebookinfo = 1, coefficientsize = 0;
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u32 csi_param;
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rtw_dbg(rtwdev, RTW_DBG_BF, "config as an mu bfee\n");
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csi_param = (u16)((coefficientsize << 10) |
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(codebookinfo << 8) |
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(grouping << 6) |
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(nr_index << 3) |
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nc_index);
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rtw_dbg(rtwdev, RTW_DBG_BF, "nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n",
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nc_index, nr_index, grouping, codebookinfo,
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coefficientsize);
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param.paid = bfee->p_aid;
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param.csi_para = csi_param;
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param.my_aid = bfee->aid & 0xfff;
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param.csi_length_sel = HAL_CSI_SEG_4K;
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ether_addr_copy(param.bfer_address, bfee->mac_addr);
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rtw_bf_init_bfer_entry_mu(rtwdev, ¶m);
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bf_info->cur_csi_rpt_rate = DESC_RATE6M;
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rtw_bf_cfg_sounding(rtwdev, vif, DESC_RATE6M);
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/* accept action_no_ack */
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rtw_write16_set(rtwdev, REG_RXFLTMAP0, BIT_RXFLTMAP0_ACTIONNOACK);
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/* accept NDPA and BF report poll */
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rtw_write16_set(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF);
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}
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EXPORT_SYMBOL(rtw_bf_enable_bfee_mu);
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void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev,
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struct rtw_bfee *bfee)
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{
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struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
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rtw_dbg(rtwdev, RTW_DBG_BF, "remove as a su bfee\n");
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rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
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RTW_SND_CTRL_REMOVE);
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switch (bfee->su_reg_index) {
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case 0:
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rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
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rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
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rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, 0);
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break;
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case 1:
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rtw_write32(rtwdev, REG_ASSOCIATED_BFMER1_INFO, 0);
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rtw_write16(rtwdev, REG_ASSOCIATED_BFMER1_INFO + 4, 0);
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rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20 + 2, 0);
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break;
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}
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clear_bit(bfee->su_reg_index, bfinfo->bfer_su_reg_maping);
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bfee->su_reg_index = 0xFF;
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}
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EXPORT_SYMBOL(rtw_bf_remove_bfee_su);
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void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev,
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struct rtw_bfee *bfee)
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{
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struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
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rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
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RTW_SND_CTRL_REMOVE);
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rtw_bf_del_bfer_entry_mu(rtwdev);
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if (bfinfo->bfer_su_cnt == 0 && bfinfo->bfer_mu_cnt == 0)
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rtw_bf_del_sounding(rtwdev);
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}
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EXPORT_SYMBOL(rtw_bf_remove_bfee_mu);
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void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
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struct ieee80211_bss_conf *conf)
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{
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struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
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struct rtw_bfee *bfee = &rtwvif->bfee;
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struct cfg_mumimo_para param;
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if (bfee->role != RTW_BFEE_MU) {
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rtw_dbg(rtwdev, RTW_DBG_BF, "this vif is not mu bfee\n");
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return;
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}
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param.grouping_bitmap = 0;
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param.mu_tx_en = 0;
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memset(param.sounding_sts, 0, 6);
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memcpy(param.given_gid_tab, conf->mu_group.membership, 8);
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memcpy(param.given_user_pos, conf->mu_group.position, 16);
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rtw_dbg(rtwdev, RTW_DBG_BF, "STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
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param.given_gid_tab[0], param.given_user_pos[0],
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param.given_user_pos[1]);
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rtw_dbg(rtwdev, RTW_DBG_BF, "STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
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param.given_gid_tab[1], param.given_user_pos[2],
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param.given_user_pos[3]);
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rtw_bf_cfg_mu_bfee(rtwdev, ¶m);
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}
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EXPORT_SYMBOL(rtw_bf_set_gid_table);
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void rtw_bf_phy_init(struct rtw_dev *rtwdev)
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{
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u8 tmp8;
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u32 tmp32;
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u8 retry_limit = 0xA;
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u8 ndpa_rate = 0x10;
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u8 ack_policy = 3;
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tmp32 = rtw_read32(rtwdev, REG_MU_TX_CTL);
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/* Enable P1 aggr new packet according to P0 transfer time */
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tmp32 |= BIT_MU_P1_WAIT_STATE_EN;
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/* MU Retry Limit */
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tmp32 &= ~BIT_MASK_R_MU_RL;
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tmp32 |= (retry_limit << BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL;
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/* Disable Tx MU-MIMO until sounding done */
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tmp32 &= ~BIT_EN_MU_MIMO;
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/* Clear validity of MU STAs */
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tmp32 &= ~BIT_MASK_R_MU_TABLE_VALID;
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rtw_write32(rtwdev, REG_MU_TX_CTL, tmp32);
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/* MU-MIMO Option as default value */
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tmp8 = ack_policy << BIT_SHIFT_WMAC_TXMU_ACKPOLICY;
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tmp8 |= BIT_WMAC_TXMU_ACKPOLICY_EN;
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rtw_write8(rtwdev, REG_WMAC_MU_BF_OPTION, tmp8);
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/* MU-MIMO Control as default value */
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rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
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/* Set MU NDPA rate & BW source */
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rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER);
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/* Set NDPA Rate */
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rtw_write8(rtwdev, REG_NDPA_OPT_CTRL, ndpa_rate);
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rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE,
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DESC_RATE6M);
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}
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EXPORT_SYMBOL(rtw_bf_phy_init);
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void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
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u8 fixrate_en, u8 *new_rate)
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{
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u32 csi_cfg;
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u16 cur_rrsr;
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csi_cfg = rtw_read32(rtwdev, REG_BBPSF_CTRL) & ~BIT_MASK_CSI_RATE;
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cur_rrsr = rtw_read16(rtwdev, REG_RRSR);
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if (rssi >= 40) {
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if (cur_rate != DESC_RATE54M) {
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cur_rrsr |= BIT(DESC_RATE54M);
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csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
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BIT_SHIFT_CSI_RATE;
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rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
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rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
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}
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*new_rate = DESC_RATE54M;
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} else {
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if (cur_rate != DESC_RATE24M) {
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cur_rrsr &= ~BIT(DESC_RATE54M);
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csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
|
|
BIT_SHIFT_CSI_RATE;
|
|
rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
|
|
rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
|
|
}
|
|
*new_rate = DESC_RATE24M;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(rtw_bf_cfg_csi_rate);
|