599 lines
17 KiB
C
599 lines
17 KiB
C
// SPDX-License-Identifier: (GPL-2.0)
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/*
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* Microchip coreQSPI QSPI controller driver
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*
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* Copyright (C) 2018-2022 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
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*
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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/*
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* QSPI Control register mask defines
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*/
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#define CONTROL_ENABLE BIT(0)
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#define CONTROL_MASTER BIT(1)
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#define CONTROL_XIP BIT(2)
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#define CONTROL_XIPADDR BIT(3)
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#define CONTROL_CLKIDLE BIT(10)
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#define CONTROL_SAMPLE_MASK GENMASK(12, 11)
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#define CONTROL_MODE0 BIT(13)
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#define CONTROL_MODE12_MASK GENMASK(15, 14)
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#define CONTROL_MODE12_EX_RO BIT(14)
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#define CONTROL_MODE12_EX_RW BIT(15)
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#define CONTROL_MODE12_FULL GENMASK(15, 14)
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#define CONTROL_FLAGSX4 BIT(16)
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#define CONTROL_CLKRATE_MASK GENMASK(27, 24)
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#define CONTROL_CLKRATE_SHIFT 24
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/*
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* QSPI Frames register mask defines
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*/
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#define FRAMES_TOTALBYTES_MASK GENMASK(15, 0)
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#define FRAMES_CMDBYTES_MASK GENMASK(24, 16)
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#define FRAMES_CMDBYTES_SHIFT 16
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#define FRAMES_SHIFT 25
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#define FRAMES_IDLE_MASK GENMASK(29, 26)
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#define FRAMES_IDLE_SHIFT 26
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#define FRAMES_FLAGBYTE BIT(30)
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#define FRAMES_FLAGWORD BIT(31)
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/*
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* QSPI Interrupt Enable register mask defines
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*/
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#define IEN_TXDONE BIT(0)
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#define IEN_RXDONE BIT(1)
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#define IEN_RXAVAILABLE BIT(2)
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#define IEN_TXAVAILABLE BIT(3)
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#define IEN_RXFIFOEMPTY BIT(4)
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#define IEN_TXFIFOFULL BIT(5)
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/*
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* QSPI Status register mask defines
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*/
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#define STATUS_TXDONE BIT(0)
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#define STATUS_RXDONE BIT(1)
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#define STATUS_RXAVAILABLE BIT(2)
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#define STATUS_TXAVAILABLE BIT(3)
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#define STATUS_RXFIFOEMPTY BIT(4)
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#define STATUS_TXFIFOFULL BIT(5)
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#define STATUS_READY BIT(7)
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#define STATUS_FLAGSX4 BIT(8)
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#define STATUS_MASK GENMASK(8, 0)
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#define BYTESUPPER_MASK GENMASK(31, 16)
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#define BYTESLOWER_MASK GENMASK(15, 0)
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#define MAX_DIVIDER 16
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#define MIN_DIVIDER 0
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#define MAX_DATA_CMD_LEN 256
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/* QSPI ready time out value */
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#define TIMEOUT_MS 500
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/*
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* QSPI Register offsets.
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*/
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#define REG_CONTROL (0x00)
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#define REG_FRAMES (0x04)
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#define REG_IEN (0x0c)
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#define REG_STATUS (0x10)
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#define REG_DIRECT_ACCESS (0x14)
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#define REG_UPPER_ACCESS (0x18)
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#define REG_RX_DATA (0x40)
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#define REG_TX_DATA (0x44)
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#define REG_X4_RX_DATA (0x48)
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#define REG_X4_TX_DATA (0x4c)
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#define REG_FRAMESUP (0x50)
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/**
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* struct mchp_coreqspi - Defines qspi driver instance
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* @regs: Virtual address of the QSPI controller registers
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* @clk: QSPI Operating clock
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* @data_completion: completion structure
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* @op_lock: lock access to the device
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* @txbuf: TX buffer
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* @rxbuf: RX buffer
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* @irq: IRQ number
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* @tx_len: Number of bytes left to transfer
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* @rx_len: Number of bytes left to receive
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*/
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struct mchp_coreqspi {
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void __iomem *regs;
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struct clk *clk;
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struct completion data_completion;
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struct mutex op_lock; /* lock access to the device */
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u8 *txbuf;
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u8 *rxbuf;
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int irq;
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int tx_len;
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int rx_len;
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};
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static int mchp_coreqspi_set_mode(struct mchp_coreqspi *qspi, const struct spi_mem_op *op)
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{
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u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
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/*
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* The operating mode can be configured based on the command that needs to be send.
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* bits[15:14]: Sets whether multiple bit SPI operates in normal, extended or full modes.
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* 00: Normal (single DQ0 TX and single DQ1 RX lines)
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* 01: Extended RO (command and address bytes on DQ0 only)
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* 10: Extended RW (command byte on DQ0 only)
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* 11: Full. (command and address are on all DQ lines)
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* bit[13]: Sets whether multiple bit SPI uses 2 or 4 bits of data
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* 0: 2-bits (BSPI)
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* 1: 4-bits (QSPI)
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*/
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if (op->data.buswidth == 4 || op->data.buswidth == 2) {
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control &= ~CONTROL_MODE12_MASK;
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if (op->cmd.buswidth == 1 && (op->addr.buswidth == 1 || op->addr.buswidth == 0))
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control |= CONTROL_MODE12_EX_RO;
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else if (op->cmd.buswidth == 1)
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control |= CONTROL_MODE12_EX_RW;
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else
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control |= CONTROL_MODE12_FULL;
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control |= CONTROL_MODE0;
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} else {
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control &= ~(CONTROL_MODE12_MASK |
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CONTROL_MODE0);
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}
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writel_relaxed(control, qspi->regs + REG_CONTROL);
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return 0;
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}
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static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi)
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{
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u32 control, data;
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if (!qspi->rx_len)
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return;
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control = readl_relaxed(qspi->regs + REG_CONTROL);
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/*
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* Read 4-bytes from the SPI FIFO in single transaction and then read
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* the reamaining data byte wise.
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*/
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control |= CONTROL_FLAGSX4;
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writel_relaxed(control, qspi->regs + REG_CONTROL);
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while (qspi->rx_len >= 4) {
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while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
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;
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data = readl_relaxed(qspi->regs + REG_X4_RX_DATA);
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*(u32 *)qspi->rxbuf = data;
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qspi->rxbuf += 4;
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qspi->rx_len -= 4;
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}
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control &= ~CONTROL_FLAGSX4;
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writel_relaxed(control, qspi->regs + REG_CONTROL);
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while (qspi->rx_len--) {
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while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
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;
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data = readl_relaxed(qspi->regs + REG_RX_DATA);
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*qspi->rxbuf++ = (data & 0xFF);
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}
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}
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static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi, bool word)
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{
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u32 control, data;
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control = readl_relaxed(qspi->regs + REG_CONTROL);
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control |= CONTROL_FLAGSX4;
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writel_relaxed(control, qspi->regs + REG_CONTROL);
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while (qspi->tx_len >= 4) {
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while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
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;
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data = *(u32 *)qspi->txbuf;
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qspi->txbuf += 4;
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qspi->tx_len -= 4;
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writel_relaxed(data, qspi->regs + REG_X4_TX_DATA);
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}
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control &= ~CONTROL_FLAGSX4;
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writel_relaxed(control, qspi->regs + REG_CONTROL);
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while (qspi->tx_len--) {
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while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
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;
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data = *qspi->txbuf++;
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writel_relaxed(data, qspi->regs + REG_TX_DATA);
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}
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}
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static void mchp_coreqspi_enable_ints(struct mchp_coreqspi *qspi)
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{
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u32 mask = IEN_TXDONE |
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IEN_RXDONE |
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IEN_RXAVAILABLE;
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writel_relaxed(mask, qspi->regs + REG_IEN);
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}
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static void mchp_coreqspi_disable_ints(struct mchp_coreqspi *qspi)
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{
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writel_relaxed(0, qspi->regs + REG_IEN);
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}
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static irqreturn_t mchp_coreqspi_isr(int irq, void *dev_id)
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{
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struct mchp_coreqspi *qspi = (struct mchp_coreqspi *)dev_id;
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irqreturn_t ret = IRQ_NONE;
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int intfield = readl_relaxed(qspi->regs + REG_STATUS) & STATUS_MASK;
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if (intfield == 0)
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return ret;
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if (intfield & IEN_TXDONE) {
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writel_relaxed(IEN_TXDONE, qspi->regs + REG_STATUS);
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ret = IRQ_HANDLED;
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}
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if (intfield & IEN_RXAVAILABLE) {
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writel_relaxed(IEN_RXAVAILABLE, qspi->regs + REG_STATUS);
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mchp_coreqspi_read_op(qspi);
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ret = IRQ_HANDLED;
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}
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if (intfield & IEN_RXDONE) {
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writel_relaxed(IEN_RXDONE, qspi->regs + REG_STATUS);
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complete(&qspi->data_completion);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_device *spi)
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{
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unsigned long clk_hz;
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u32 control, baud_rate_val = 0;
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clk_hz = clk_get_rate(qspi->clk);
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if (!clk_hz)
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return -EINVAL;
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baud_rate_val = DIV_ROUND_UP(clk_hz, 2 * spi->max_speed_hz);
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if (baud_rate_val > MAX_DIVIDER || baud_rate_val < MIN_DIVIDER) {
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dev_err(&spi->dev,
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"could not configure the clock for spi clock %d Hz & system clock %ld Hz\n",
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spi->max_speed_hz, clk_hz);
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return -EINVAL;
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}
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control = readl_relaxed(qspi->regs + REG_CONTROL);
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control |= baud_rate_val << CONTROL_CLKRATE_SHIFT;
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writel_relaxed(control, qspi->regs + REG_CONTROL);
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control = readl_relaxed(qspi->regs + REG_CONTROL);
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if ((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA))
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control |= CONTROL_CLKIDLE;
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else
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control &= ~CONTROL_CLKIDLE;
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writel_relaxed(control, qspi->regs + REG_CONTROL);
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return 0;
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}
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static int mchp_coreqspi_setup_op(struct spi_device *spi_dev)
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{
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struct spi_controller *ctlr = spi_dev->master;
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struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
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u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
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control |= (CONTROL_MASTER | CONTROL_ENABLE);
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control &= ~CONTROL_CLKIDLE;
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writel_relaxed(control, qspi->regs + REG_CONTROL);
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return 0;
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}
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static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const struct spi_mem_op *op)
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{
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u32 idle_cycles = 0;
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int total_bytes, cmd_bytes, frames, ctrl;
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cmd_bytes = op->cmd.nbytes + op->addr.nbytes;
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total_bytes = cmd_bytes + op->data.nbytes;
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/*
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* As per the coreQSPI IP spec,the number of command and data bytes are
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* controlled by the frames register for each SPI sequence. This supports
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* the SPI flash memory read and writes sequences as below. so configure
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* the cmd and total bytes accordingly.
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* ---------------------------------------------------------------------
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* TOTAL BYTES | CMD BYTES | What happens |
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* ______________________________________________________________________
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* | | |
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* 1 | 1 | The SPI core will transmit a single byte |
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* | | and receive data is discarded |
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* | | |
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* 1 | 0 | The SPI core will transmit a single byte |
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* | | and return a single byte |
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* | | |
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* 10 | 4 | The SPI core will transmit 4 command |
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* | | bytes discarding the receive data and |
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* | | transmits 6 dummy bytes returning the 6 |
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* | | received bytes and return a single byte |
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* | | |
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* 10 | 10 | The SPI core will transmit 10 command |
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* | | |
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* 10 | 0 | The SPI core will transmit 10 command |
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* | | bytes and returning 10 received bytes |
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* ______________________________________________________________________
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*/
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if (!(op->data.dir == SPI_MEM_DATA_IN))
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cmd_bytes = total_bytes;
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frames = total_bytes & BYTESUPPER_MASK;
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writel_relaxed(frames, qspi->regs + REG_FRAMESUP);
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frames = total_bytes & BYTESLOWER_MASK;
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frames |= cmd_bytes << FRAMES_CMDBYTES_SHIFT;
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if (op->dummy.buswidth)
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idle_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
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frames |= idle_cycles << FRAMES_IDLE_SHIFT;
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ctrl = readl_relaxed(qspi->regs + REG_CONTROL);
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if (ctrl & CONTROL_MODE12_MASK)
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frames |= (1 << FRAMES_SHIFT);
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frames |= FRAMES_FLAGWORD;
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writel_relaxed(frames, qspi->regs + REG_FRAMES);
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}
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static int mchp_qspi_wait_for_ready(struct spi_mem *mem)
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{
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struct mchp_coreqspi *qspi = spi_controller_get_devdata
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(mem->spi->master);
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u32 status;
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int ret;
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ret = readl_poll_timeout(qspi->regs + REG_STATUS, status,
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(status & STATUS_READY), 0,
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TIMEOUT_MS);
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if (ret) {
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dev_err(&mem->spi->dev,
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"Timeout waiting on QSPI ready.\n");
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return -ETIMEDOUT;
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}
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return ret;
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}
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static int mchp_coreqspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct mchp_coreqspi *qspi = spi_controller_get_devdata
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(mem->spi->master);
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u32 address = op->addr.val;
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u8 opcode = op->cmd.opcode;
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u8 opaddr[5];
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int err, i;
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mutex_lock(&qspi->op_lock);
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err = mchp_qspi_wait_for_ready(mem);
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if (err)
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goto error;
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err = mchp_coreqspi_setup_clock(qspi, mem->spi);
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if (err)
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goto error;
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err = mchp_coreqspi_set_mode(qspi, op);
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if (err)
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goto error;
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reinit_completion(&qspi->data_completion);
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mchp_coreqspi_config_op(qspi, op);
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if (op->cmd.opcode) {
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qspi->txbuf = &opcode;
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qspi->rxbuf = NULL;
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qspi->tx_len = op->cmd.nbytes;
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qspi->rx_len = 0;
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mchp_coreqspi_write_op(qspi, false);
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}
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qspi->txbuf = &opaddr[0];
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if (op->addr.nbytes) {
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for (i = 0; i < op->addr.nbytes; i++)
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qspi->txbuf[i] = address >> (8 * (op->addr.nbytes - i - 1));
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qspi->rxbuf = NULL;
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qspi->tx_len = op->addr.nbytes;
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qspi->rx_len = 0;
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mchp_coreqspi_write_op(qspi, false);
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}
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if (op->data.nbytes) {
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if (op->data.dir == SPI_MEM_DATA_OUT) {
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qspi->txbuf = (u8 *)op->data.buf.out;
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qspi->rxbuf = NULL;
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qspi->rx_len = 0;
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qspi->tx_len = op->data.nbytes;
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mchp_coreqspi_write_op(qspi, true);
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} else {
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qspi->txbuf = NULL;
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qspi->rxbuf = (u8 *)op->data.buf.in;
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qspi->rx_len = op->data.nbytes;
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qspi->tx_len = 0;
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}
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}
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mchp_coreqspi_enable_ints(qspi);
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if (!wait_for_completion_timeout(&qspi->data_completion, msecs_to_jiffies(1000)))
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err = -ETIMEDOUT;
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error:
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mutex_unlock(&qspi->op_lock);
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mchp_coreqspi_disable_ints(qspi);
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return err;
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}
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static bool mchp_coreqspi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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if (!spi_mem_default_supports_op(mem, op))
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return false;
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if ((op->data.buswidth == 4 || op->data.buswidth == 2) &&
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(op->cmd.buswidth == 1 && (op->addr.buswidth == 1 || op->addr.buswidth == 0))) {
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/*
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* If the command and address are on DQ0 only, then this
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* controller doesn't support sending data on dual and
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* quad lines. but it supports reading data on dual and
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* quad lines with same configuration as command and
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* address on DQ0.
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* i.e. The control register[15:13] :EX_RO(read only) is
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* meant only for the command and address are on DQ0 but
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* not to write data, it is just to read.
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* Ex: 0x34h is Quad Load Program Data which is not
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* supported. Then the spi-mem layer will iterate over
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* each command and it will chose the supported one.
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*/
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if (op->data.dir == SPI_MEM_DATA_OUT)
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return false;
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}
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return true;
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}
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static int mchp_coreqspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
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{
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if (op->data.dir == SPI_MEM_DATA_OUT || op->data.dir == SPI_MEM_DATA_IN) {
|
|
if (op->data.nbytes > MAX_DATA_CMD_LEN)
|
|
op->data.nbytes = MAX_DATA_CMD_LEN;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops mchp_coreqspi_mem_ops = {
|
|
.adjust_op_size = mchp_coreqspi_adjust_op_size,
|
|
.supports_op = mchp_coreqspi_supports_op,
|
|
.exec_op = mchp_coreqspi_exec_op,
|
|
};
|
|
|
|
static int mchp_coreqspi_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_controller *ctlr;
|
|
struct mchp_coreqspi *qspi;
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
int ret;
|
|
|
|
ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*qspi));
|
|
if (!ctlr)
|
|
return dev_err_probe(&pdev->dev, -ENOMEM,
|
|
"unable to allocate master for QSPI controller\n");
|
|
|
|
qspi = spi_controller_get_devdata(ctlr);
|
|
platform_set_drvdata(pdev, qspi);
|
|
|
|
qspi->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(qspi->regs))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(qspi->regs),
|
|
"failed to map registers\n");
|
|
|
|
qspi->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(qspi->clk))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(qspi->clk),
|
|
"could not get clock\n");
|
|
|
|
ret = clk_prepare_enable(qspi->clk);
|
|
if (ret)
|
|
return dev_err_probe(&pdev->dev, ret,
|
|
"failed to enable clock\n");
|
|
|
|
init_completion(&qspi->data_completion);
|
|
mutex_init(&qspi->op_lock);
|
|
|
|
qspi->irq = platform_get_irq(pdev, 0);
|
|
if (qspi->irq < 0) {
|
|
ret = qspi->irq;
|
|
goto out;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr,
|
|
IRQF_SHARED, pdev->name, qspi);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "request_irq failed %d\n", ret);
|
|
goto out;
|
|
}
|
|
|
|
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
ctlr->mem_ops = &mchp_coreqspi_mem_ops;
|
|
ctlr->setup = mchp_coreqspi_setup_op;
|
|
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
|
|
SPI_TX_DUAL | SPI_TX_QUAD;
|
|
ctlr->dev.of_node = np;
|
|
|
|
ret = devm_spi_register_controller(&pdev->dev, ctlr);
|
|
if (ret) {
|
|
dev_err_probe(&pdev->dev, ret,
|
|
"spi_register_controller failed\n");
|
|
goto out;
|
|
}
|
|
|
|
return 0;
|
|
|
|
out:
|
|
clk_disable_unprepare(qspi->clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void mchp_coreqspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct mchp_coreqspi *qspi = platform_get_drvdata(pdev);
|
|
u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
|
|
|
|
mchp_coreqspi_disable_ints(qspi);
|
|
control &= ~CONTROL_ENABLE;
|
|
writel_relaxed(control, qspi->regs + REG_CONTROL);
|
|
clk_disable_unprepare(qspi->clk);
|
|
}
|
|
|
|
static const struct of_device_id mchp_coreqspi_of_match[] = {
|
|
{ .compatible = "microchip,coreqspi-rtl-v2" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mchp_coreqspi_of_match);
|
|
|
|
static struct platform_driver mchp_coreqspi_driver = {
|
|
.probe = mchp_coreqspi_probe,
|
|
.driver = {
|
|
.name = "microchip,coreqspi",
|
|
.of_match_table = mchp_coreqspi_of_match,
|
|
},
|
|
.remove_new = mchp_coreqspi_remove,
|
|
};
|
|
module_platform_driver(mchp_coreqspi_driver);
|
|
|
|
MODULE_AUTHOR("Naga Sureshkumar Relli <nagasuresh.relli@microchip.com");
|
|
MODULE_DESCRIPTION("Microchip coreQSPI QSPI controller driver");
|
|
MODULE_LICENSE("GPL");
|