546 lines
12 KiB
C
546 lines
12 KiB
C
/*
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* MicroWire interface driver for OMAP
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*
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* Copyright 2003 MontaVista Software Inc. <source@mvista.com>
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*
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* Ported to 2.6 OMAP uwire interface.
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* Copyright (C) 2004 Texas Instruments.
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*
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* Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
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*
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* Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
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* Copyright (C) 2006 Nokia
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*
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* Many updates by Imre Deak <imre.deak@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <asm/mach-types.h>
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#include <linux/soc/ti/omap1-io.h>
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#include <linux/soc/ti/omap1-soc.h>
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#include <linux/soc/ti/omap1-mux.h>
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/* FIXME address is now a platform device resource,
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* and irqs should show there too...
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*/
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#define UWIRE_BASE_PHYS 0xFFFB3000
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/* uWire Registers: */
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#define UWIRE_IO_SIZE 0x20
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#define UWIRE_TDR 0x00
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#define UWIRE_RDR 0x00
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#define UWIRE_CSR 0x01
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#define UWIRE_SR1 0x02
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#define UWIRE_SR2 0x03
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#define UWIRE_SR3 0x04
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#define UWIRE_SR4 0x05
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#define UWIRE_SR5 0x06
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/* CSR bits */
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#define RDRB (1 << 15)
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#define CSRB (1 << 14)
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#define START (1 << 13)
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#define CS_CMD (1 << 12)
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/* SR1 or SR2 bits */
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#define UWIRE_READ_FALLING_EDGE 0x0001
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#define UWIRE_READ_RISING_EDGE 0x0000
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#define UWIRE_WRITE_FALLING_EDGE 0x0000
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#define UWIRE_WRITE_RISING_EDGE 0x0002
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#define UWIRE_CS_ACTIVE_LOW 0x0000
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#define UWIRE_CS_ACTIVE_HIGH 0x0004
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#define UWIRE_FREQ_DIV_2 0x0000
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#define UWIRE_FREQ_DIV_4 0x0008
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#define UWIRE_FREQ_DIV_8 0x0010
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#define UWIRE_CHK_READY 0x0020
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#define UWIRE_CLK_INVERTED 0x0040
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struct uwire_spi {
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struct spi_bitbang bitbang;
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struct clk *ck;
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};
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struct uwire_state {
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unsigned div1_idx;
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};
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/* REVISIT compile time constant for idx_shift? */
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/*
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* Or, put it in a structure which is used throughout the driver;
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* that avoids having to issue two loads for each bit of static data.
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*/
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static unsigned int uwire_idx_shift = 2;
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static void __iomem *uwire_base;
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static inline void uwire_write_reg(int idx, u16 val)
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{
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__raw_writew(val, uwire_base + (idx << uwire_idx_shift));
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}
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static inline u16 uwire_read_reg(int idx)
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{
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return __raw_readw(uwire_base + (idx << uwire_idx_shift));
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}
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static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
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{
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u16 w, val = 0;
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int shift, reg;
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if (flags & UWIRE_CLK_INVERTED)
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val ^= 0x03;
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val = flags & 0x3f;
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if (cs & 1)
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shift = 6;
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else
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shift = 0;
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if (cs <= 1)
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reg = UWIRE_SR1;
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else
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reg = UWIRE_SR2;
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w = uwire_read_reg(reg);
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w &= ~(0x3f << shift);
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w |= val << shift;
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uwire_write_reg(reg, w);
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}
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static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
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{
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u16 w;
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int c = 0;
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unsigned long max_jiffies = jiffies + HZ;
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for (;;) {
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w = uwire_read_reg(UWIRE_CSR);
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if ((w & mask) == val)
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break;
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if (time_after(jiffies, max_jiffies)) {
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printk(KERN_ERR "%s: timeout. reg=%#06x "
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"mask=%#06x val=%#06x\n",
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__func__, w, mask, val);
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return -1;
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}
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c++;
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if (might_not_catch && c > 64)
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break;
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}
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return 0;
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}
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static void uwire_set_clk1_div(int div1_idx)
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{
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u16 w;
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w = uwire_read_reg(UWIRE_SR3);
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w &= ~(0x03 << 1);
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w |= div1_idx << 1;
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uwire_write_reg(UWIRE_SR3, w);
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}
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static void uwire_chipselect(struct spi_device *spi, int value)
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{
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struct uwire_state *ust = spi->controller_state;
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u16 w;
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int old_cs;
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BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
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w = uwire_read_reg(UWIRE_CSR);
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old_cs = (w >> 10) & 0x03;
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if (value == BITBANG_CS_INACTIVE || old_cs != spi_get_chipselect(spi, 0)) {
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/* Deselect this CS, or the previous CS */
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w &= ~CS_CMD;
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uwire_write_reg(UWIRE_CSR, w);
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}
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/* activate specfied chipselect */
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if (value == BITBANG_CS_ACTIVE) {
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uwire_set_clk1_div(ust->div1_idx);
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/* invert clock? */
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if (spi->mode & SPI_CPOL)
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uwire_write_reg(UWIRE_SR4, 1);
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else
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uwire_write_reg(UWIRE_SR4, 0);
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w = spi_get_chipselect(spi, 0) << 10;
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w |= CS_CMD;
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uwire_write_reg(UWIRE_CSR, w);
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}
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}
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static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
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{
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unsigned len = t->len;
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unsigned bits = t->bits_per_word;
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unsigned bytes;
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u16 val, w;
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int status = 0;
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if (!t->tx_buf && !t->rx_buf)
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return 0;
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w = spi_get_chipselect(spi, 0) << 10;
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w |= CS_CMD;
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if (t->tx_buf) {
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const u8 *buf = t->tx_buf;
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/* NOTE: DMA could be used for TX transfers */
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/* write one or two bytes at a time */
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while (len >= 1) {
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/* tx bit 15 is first sent; we byteswap multibyte words
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* (msb-first) on the way out from memory.
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*/
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val = *buf++;
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if (bits > 8) {
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bytes = 2;
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val |= *buf++ << 8;
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} else
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bytes = 1;
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val <<= 16 - bits;
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#ifdef VERBOSE
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pr_debug("%s: write-%d =%04x\n",
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dev_name(&spi->dev), bits, val);
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#endif
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if (wait_uwire_csr_flag(CSRB, 0, 0))
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goto eio;
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uwire_write_reg(UWIRE_TDR, val);
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/* start write */
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val = START | w | (bits << 5);
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uwire_write_reg(UWIRE_CSR, val);
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len -= bytes;
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/* Wait till write actually starts.
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* This is needed with MPU clock 60+ MHz.
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* REVISIT: we may not have time to catch it...
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*/
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if (wait_uwire_csr_flag(CSRB, CSRB, 1))
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goto eio;
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status += bytes;
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}
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/* REVISIT: save this for later to get more i/o overlap */
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if (wait_uwire_csr_flag(CSRB, 0, 0))
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goto eio;
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} else if (t->rx_buf) {
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u8 *buf = t->rx_buf;
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/* read one or two bytes at a time */
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while (len) {
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if (bits > 8) {
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bytes = 2;
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} else
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bytes = 1;
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/* start read */
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val = START | w | (bits << 0);
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uwire_write_reg(UWIRE_CSR, val);
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len -= bytes;
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/* Wait till read actually starts */
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(void) wait_uwire_csr_flag(CSRB, CSRB, 1);
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if (wait_uwire_csr_flag(RDRB | CSRB,
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RDRB, 0))
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goto eio;
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/* rx bit 0 is last received; multibyte words will
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* be properly byteswapped on the way to memory.
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*/
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val = uwire_read_reg(UWIRE_RDR);
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val &= (1 << bits) - 1;
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*buf++ = (u8) val;
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if (bytes == 2)
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*buf++ = val >> 8;
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status += bytes;
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#ifdef VERBOSE
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pr_debug("%s: read-%d =%04x\n",
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dev_name(&spi->dev), bits, val);
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#endif
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}
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}
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return status;
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eio:
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return -EIO;
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}
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static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
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{
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struct uwire_state *ust = spi->controller_state;
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struct uwire_spi *uwire;
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unsigned flags = 0;
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unsigned hz;
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unsigned long rate;
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int div1_idx;
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int div1;
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int div2;
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int status;
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uwire = spi_master_get_devdata(spi->master);
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/* mode 0..3, clock inverted separately;
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* standard nCS signaling;
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* don't treat DI=high as "not ready"
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*/
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if (spi->mode & SPI_CS_HIGH)
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flags |= UWIRE_CS_ACTIVE_HIGH;
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if (spi->mode & SPI_CPOL)
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flags |= UWIRE_CLK_INVERTED;
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switch (spi->mode & SPI_MODE_X_MASK) {
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case SPI_MODE_0:
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case SPI_MODE_3:
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flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
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break;
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case SPI_MODE_1:
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case SPI_MODE_2:
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flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
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break;
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}
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/* assume it's already enabled */
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rate = clk_get_rate(uwire->ck);
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if (t != NULL)
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hz = t->speed_hz;
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else
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hz = spi->max_speed_hz;
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if (!hz) {
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pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
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status = -EINVAL;
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goto done;
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}
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/* F_INT = mpu_xor_clk / DIV1 */
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for (div1_idx = 0; div1_idx < 4; div1_idx++) {
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switch (div1_idx) {
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case 0:
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div1 = 2;
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break;
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case 1:
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div1 = 4;
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break;
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case 2:
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div1 = 7;
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break;
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default:
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case 3:
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div1 = 10;
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break;
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}
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div2 = (rate / div1 + hz - 1) / hz;
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if (div2 <= 8)
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break;
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}
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if (div1_idx == 4) {
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pr_debug("%s: lowest clock %ld, need %d\n",
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dev_name(&spi->dev), rate / 10 / 8, hz);
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status = -EDOM;
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goto done;
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}
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/* we have to cache this and reset in uwire_chipselect as this is a
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* global parameter and another uwire device can change it under
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* us */
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ust->div1_idx = div1_idx;
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uwire_set_clk1_div(div1_idx);
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rate /= div1;
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switch (div2) {
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case 0:
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case 1:
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case 2:
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flags |= UWIRE_FREQ_DIV_2;
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rate /= 2;
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break;
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case 3:
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case 4:
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flags |= UWIRE_FREQ_DIV_4;
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rate /= 4;
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break;
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case 5:
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case 6:
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case 7:
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case 8:
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flags |= UWIRE_FREQ_DIV_8;
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rate /= 8;
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break;
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}
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omap_uwire_configure_mode(spi_get_chipselect(spi, 0), flags);
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pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
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__func__, flags,
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clk_get_rate(uwire->ck) / 1000,
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rate / 1000);
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status = 0;
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done:
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return status;
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}
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static int uwire_setup(struct spi_device *spi)
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{
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struct uwire_state *ust = spi->controller_state;
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bool initial_setup = false;
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int status;
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if (ust == NULL) {
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ust = kzalloc(sizeof(*ust), GFP_KERNEL);
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if (ust == NULL)
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return -ENOMEM;
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spi->controller_state = ust;
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initial_setup = true;
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}
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status = uwire_setup_transfer(spi, NULL);
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if (status && initial_setup)
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kfree(ust);
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return status;
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}
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static void uwire_cleanup(struct spi_device *spi)
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{
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kfree(spi->controller_state);
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}
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static void uwire_off(struct uwire_spi *uwire)
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{
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uwire_write_reg(UWIRE_SR3, 0);
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clk_disable_unprepare(uwire->ck);
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spi_master_put(uwire->bitbang.master);
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}
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static int uwire_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct uwire_spi *uwire;
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int status;
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master = spi_alloc_master(&pdev->dev, sizeof(*uwire));
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if (!master)
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return -ENODEV;
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uwire = spi_master_get_devdata(master);
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uwire_base = devm_ioremap(&pdev->dev, UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
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if (!uwire_base) {
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dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
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spi_master_put(master);
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return -ENOMEM;
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}
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platform_set_drvdata(pdev, uwire);
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uwire->ck = devm_clk_get(&pdev->dev, "fck");
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if (IS_ERR(uwire->ck)) {
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status = PTR_ERR(uwire->ck);
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dev_dbg(&pdev->dev, "no functional clock?\n");
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spi_master_put(master);
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return status;
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}
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clk_prepare_enable(uwire->ck);
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uwire_write_reg(UWIRE_SR3, 1);
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/* the spi->mode bits understood by this driver: */
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
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master->flags = SPI_MASTER_HALF_DUPLEX;
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master->bus_num = 2; /* "official" */
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master->num_chipselect = 4;
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master->setup = uwire_setup;
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master->cleanup = uwire_cleanup;
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uwire->bitbang.master = master;
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uwire->bitbang.chipselect = uwire_chipselect;
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uwire->bitbang.setup_transfer = uwire_setup_transfer;
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uwire->bitbang.txrx_bufs = uwire_txrx;
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status = spi_bitbang_start(&uwire->bitbang);
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if (status < 0) {
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uwire_off(uwire);
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}
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return status;
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}
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static void uwire_remove(struct platform_device *pdev)
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{
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struct uwire_spi *uwire = platform_get_drvdata(pdev);
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// FIXME remove all child devices, somewhere ...
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spi_bitbang_stop(&uwire->bitbang);
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uwire_off(uwire);
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}
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/* work with hotplug and coldplug */
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MODULE_ALIAS("platform:omap_uwire");
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static struct platform_driver uwire_driver = {
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.driver = {
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.name = "omap_uwire",
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},
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.probe = uwire_probe,
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.remove_new = uwire_remove,
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// suspend ... unuse ck
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// resume ... use ck
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};
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static int __init omap_uwire_init(void)
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{
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return platform_driver_register(&uwire_driver);
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}
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|
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static void __exit omap_uwire_exit(void)
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|
{
|
|
platform_driver_unregister(&uwire_driver);
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|
}
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|
|
|
subsys_initcall(omap_uwire_init);
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|
module_exit(omap_uwire_exit);
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|
|
|
MODULE_LICENSE("GPL");
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|
|