822 lines
23 KiB
C
822 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* MA35D1 serial driver
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* Copyright (C) 2023 Nuvoton Technology Corp.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/iopoll.h>
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#include <linux/serial_core.h>
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#include <linux/slab.h>
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#include <linux/tty_flip.h>
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#include <linux/units.h>
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#define MA35_UART_NR 17
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#define MA35_RBR_REG 0x00
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#define MA35_THR_REG 0x00
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#define MA35_IER_REG 0x04
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#define MA35_FCR_REG 0x08
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#define MA35_LCR_REG 0x0C
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#define MA35_MCR_REG 0x10
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#define MA35_MSR_REG 0x14
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#define MA35_FSR_REG 0x18
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#define MA35_ISR_REG 0x1C
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#define MA35_TOR_REG 0x20
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#define MA35_BAUD_REG 0x24
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#define MA35_ALTCTL_REG 0x2C
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#define MA35_FUN_SEL_REG 0x30
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#define MA35_WKCTL_REG 0x40
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#define MA35_WKSTS_REG 0x44
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/* MA35_IER_REG - Interrupt Enable Register */
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#define MA35_IER_RDA_IEN BIT(0) /* RBR Available Interrupt Enable */
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#define MA35_IER_THRE_IEN BIT(1) /* THR Empty Interrupt Enable */
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#define MA35_IER_RLS_IEN BIT(2) /* RX Line Status Interrupt Enable */
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#define MA35_IER_RTO_IEN BIT(4) /* RX Time-out Interrupt Enable */
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#define MA35_IER_BUFERR_IEN BIT(5) /* Buffer Error Interrupt Enable */
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#define MA35_IER_TIME_OUT_EN BIT(11) /* RX Buffer Time-out Counter Enable */
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#define MA35_IER_AUTO_RTS BIT(12) /* nRTS Auto-flow Control Enable */
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#define MA35_IER_AUTO_CTS BIT(13) /* nCTS Auto-flow Control Enable */
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/* MA35_FCR_REG - FIFO Control Register */
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#define MA35_FCR_RFR BIT(1) /* RX Field Software Reset */
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#define MA35_FCR_TFR BIT(2) /* TX Field Software Reset */
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#define MA35_FCR_RFITL_MASK GENMASK(7, 4) /* RX FIFO Interrupt Trigger Level */
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#define MA35_FCR_RFITL_1BYTE FIELD_PREP(MA35_FCR_RFITL_MASK, 0)
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#define MA35_FCR_RFITL_4BYTES FIELD_PREP(MA35_FCR_RFITL_MASK, 1)
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#define MA35_FCR_RFITL_8BYTES FIELD_PREP(MA35_FCR_RFITL_MASK, 2)
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#define MA35_FCR_RFITL_14BYTES FIELD_PREP(MA35_FCR_RFITL_MASK, 3)
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#define MA35_FCR_RFITL_30BYTES FIELD_PREP(MA35_FCR_RFITL_MASK, 4)
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#define MA35_FCR_RTSTL_MASK GENMASK(19, 16) /* nRTS Trigger Level */
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#define MA35_FCR_RTSTL_1BYTE FIELD_PREP(MA35_FCR_RTSTL_MASK, 0)
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#define MA35_FCR_RTSTL_4BYTES FIELD_PREP(MA35_FCR_RTSTL_MASK, 1)
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#define MA35_FCR_RTSTL_8BYTES FIELD_PREP(MA35_FCR_RTSTL_MASK, 2)
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#define MA35_FCR_RTSTL_14BYTES FIELD_PREP(MA35_FCR_RTSTL_MASK, 3)
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#define MA35_FCR_RTSTLL_30BYTES FIELD_PREP(MA35_FCR_RTSTL_MASK, 4)
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/* MA35_LCR_REG - Line Control Register */
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#define MA35_LCR_NSB BIT(2) /* Number of “STOP Bit” */
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#define MA35_LCR_PBE BIT(3) /* Parity Bit Enable */
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#define MA35_LCR_EPE BIT(4) /* Even Parity Enable */
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#define MA35_LCR_SPE BIT(5) /* Stick Parity Enable */
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#define MA35_LCR_BREAK BIT(6) /* Break Control */
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#define MA35_LCR_WLS_MASK GENMASK(1, 0) /* Word Length Selection */
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#define MA35_LCR_WLS_5BITS FIELD_PREP(MA35_LCR_WLS_MASK, 0)
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#define MA35_LCR_WLS_6BITS FIELD_PREP(MA35_LCR_WLS_MASK, 1)
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#define MA35_LCR_WLS_7BITS FIELD_PREP(MA35_LCR_WLS_MASK, 2)
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#define MA35_LCR_WLS_8BITS FIELD_PREP(MA35_LCR_WLS_MASK, 3)
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/* MA35_MCR_REG - Modem Control Register */
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#define MA35_MCR_RTS_CTRL BIT(1) /* nRTS Signal Control */
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#define MA35_MCR_RTSACTLV BIT(9) /* nRTS Pin Active Level */
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#define MA35_MCR_RTSSTS BIT(13) /* nRTS Pin Status (Read Only) */
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/* MA35_MSR_REG - Modem Status Register */
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#define MA35_MSR_CTSDETF BIT(0) /* Detect nCTS State Change Flag */
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#define MA35_MSR_CTSSTS BIT(4) /* nCTS Pin Status (Read Only) */
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#define MA35_MSR_CTSACTLV BIT(8) /* nCTS Pin Active Level */
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/* MA35_FSR_REG - FIFO Status Register */
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#define MA35_FSR_RX_OVER_IF BIT(0) /* RX Overflow Error Interrupt Flag */
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#define MA35_FSR_PEF BIT(4) /* Parity Error Flag*/
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#define MA35_FSR_FEF BIT(5) /* Framing Error Flag */
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#define MA35_FSR_BIF BIT(6) /* Break Interrupt Flag */
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#define MA35_FSR_RX_EMPTY BIT(14) /* Receiver FIFO Empty (Read Only) */
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#define MA35_FSR_RX_FULL BIT(15) /* Receiver FIFO Full (Read Only) */
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#define MA35_FSR_TX_EMPTY BIT(22) /* Transmitter FIFO Empty (Read Only) */
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#define MA35_FSR_TX_FULL BIT(23) /* Transmitter FIFO Full (Read Only) */
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#define MA35_FSR_TX_OVER_IF BIT(24) /* TX Overflow Error Interrupt Flag */
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#define MA35_FSR_TE_FLAG BIT(28) /* Transmitter Empty Flag (Read Only) */
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#define MA35_FSR_RXPTR_MSK GENMASK(13, 8) /* TX FIFO Pointer mask */
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#define MA35_FSR_TXPTR_MSK GENMASK(21, 16) /* RX FIFO Pointer mask */
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/* MA35_ISR_REG - Interrupt Status Register */
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#define MA35_ISR_RDA_IF BIT(0) /* RBR Available Interrupt Flag */
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#define MA35_ISR_THRE_IF BIT(1) /* THR Empty Interrupt Flag */
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#define MA35_ISR_RLSIF BIT(2) /* Receive Line Interrupt Flag */
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#define MA35_ISR_MODEMIF BIT(3) /* MODEM Interrupt Flag */
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#define MA35_ISR_RXTO_IF BIT(4) /* RX Time-out Interrupt Flag */
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#define MA35_ISR_BUFEIF BIT(5) /* Buffer Error Interrupt Flag */
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#define MA35_ISR_WK_IF BIT(6) /* UART Wake-up Interrupt Flag */
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#define MA35_ISR_RDAINT BIT(8) /* RBR Available Interrupt Indicator */
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#define MA35_ISR_THRE_INT BIT(9) /* THR Empty Interrupt Indicator */
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#define MA35_ISR_ALL 0xFFFFFFFF
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/* MA35_BAUD_REG - Baud Rate Divider Register */
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#define MA35_BAUD_MODE_MASK GENMASK(29, 28)
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#define MA35_BAUD_MODE0 FIELD_PREP(MA35_BAUD_MODE_MASK, 0)
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#define MA35_BAUD_MODE1 FIELD_PREP(MA35_BAUD_MODE_MASK, 2)
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#define MA35_BAUD_MODE2 FIELD_PREP(MA35_BAUD_MODE_MASK, 3)
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#define MA35_BAUD_MASK GENMASK(15, 0)
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/* MA35_ALTCTL_REG - Alternate Control/Status Register */
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#define MA35_ALTCTL_RS485AUD BIT(10) /* RS-485 Auto Direction Function */
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/* MA35_FUN_SEL_REG - Function Select Register */
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#define MA35_FUN_SEL_MASK GENMASK(2, 0)
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#define MA35_FUN_SEL_UART FIELD_PREP(MA35_FUN_SEL_MASK, 0)
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#define MA35_FUN_SEL_RS485 FIELD_PREP(MA35_FUN_SEL_MASK, 3)
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/* The constrain for MA35D1 UART baud rate divider */
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#define MA35_BAUD_DIV_MAX 0xFFFF
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#define MA35_BAUD_DIV_MIN 11
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/* UART FIFO depth */
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#define MA35_UART_FIFO_DEPTH 32
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/* UART console clock */
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#define MA35_UART_CONSOLE_CLK (24 * HZ_PER_MHZ)
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/* UART register ioremap size */
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#define MA35_UART_REG_SIZE 0x100
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/* Rx Timeout */
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#define MA35_UART_RX_TOUT 0x40
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#define MA35_IER_CONFIG (MA35_IER_RTO_IEN | MA35_IER_RDA_IEN | \
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MA35_IER_TIME_OUT_EN | MA35_IER_BUFERR_IEN)
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#define MA35_ISR_IF_CHECK (MA35_ISR_RDA_IF | MA35_ISR_RXTO_IF | \
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MA35_ISR_THRE_INT | MA35_ISR_BUFEIF)
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#define MA35_FSR_TX_BOTH_EMPTY (MA35_FSR_TE_FLAG | MA35_FSR_TX_EMPTY)
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static struct uart_driver ma35d1serial_reg;
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struct uart_ma35d1_port {
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struct uart_port port;
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struct clk *clk;
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u16 capabilities; /* port capabilities */
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u8 ier;
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u8 lcr;
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u8 mcr;
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u32 baud_rate;
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u32 console_baud_rate;
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u32 console_line;
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u32 console_int;
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};
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static struct uart_ma35d1_port ma35d1serial_ports[MA35_UART_NR];
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static struct uart_ma35d1_port *to_ma35d1_uart_port(struct uart_port *uart)
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{
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return container_of(uart, struct uart_ma35d1_port, port);
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}
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static u32 serial_in(struct uart_ma35d1_port *p, u32 offset)
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{
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return readl_relaxed(p->port.membase + offset);
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}
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static void serial_out(struct uart_ma35d1_port *p, u32 offset, u32 value)
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{
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writel_relaxed(value, p->port.membase + offset);
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}
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static void __stop_tx(struct uart_ma35d1_port *p)
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{
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u32 ier;
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ier = serial_in(p, MA35_IER_REG);
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if (ier & MA35_IER_THRE_IEN)
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serial_out(p, MA35_IER_REG, ier & ~MA35_IER_THRE_IEN);
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}
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static void ma35d1serial_stop_tx(struct uart_port *port)
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{
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struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
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__stop_tx(up);
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}
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static void transmit_chars(struct uart_ma35d1_port *up)
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{
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u32 count;
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u8 ch;
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if (uart_tx_stopped(&up->port)) {
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ma35d1serial_stop_tx(&up->port);
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return;
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}
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count = MA35_UART_FIFO_DEPTH - FIELD_GET(MA35_FSR_TXPTR_MSK,
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serial_in(up, MA35_FSR_REG));
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uart_port_tx_limited(&up->port, ch, count,
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!(serial_in(up, MA35_FSR_REG) & MA35_FSR_TX_FULL),
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serial_out(up, MA35_THR_REG, ch),
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({}));
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}
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static void ma35d1serial_start_tx(struct uart_port *port)
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{
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struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
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u32 ier;
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ier = serial_in(up, MA35_IER_REG);
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serial_out(up, MA35_IER_REG, ier & ~MA35_IER_THRE_IEN);
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transmit_chars(up);
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serial_out(up, MA35_IER_REG, ier | MA35_IER_THRE_IEN);
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}
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static void ma35d1serial_stop_rx(struct uart_port *port)
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{
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struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
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u32 ier;
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ier = serial_in(up, MA35_IER_REG);
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ier &= ~MA35_IER_RDA_IEN;
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serial_out(up, MA35_IER_REG, ier);
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}
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static void receive_chars(struct uart_ma35d1_port *up)
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{
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int max_count = 256;
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u8 ch, flag;
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u32 fsr;
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fsr = serial_in(up, MA35_FSR_REG);
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do {
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flag = TTY_NORMAL;
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up->port.icount.rx++;
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if (unlikely(fsr & (MA35_FSR_BIF | MA35_FSR_FEF |
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MA35_FSR_PEF | MA35_FSR_RX_OVER_IF))) {
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if (fsr & MA35_FSR_BIF) {
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up->port.icount.brk++;
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if (uart_handle_break(&up->port))
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continue;
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}
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if (fsr & MA35_FSR_FEF)
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up->port.icount.frame++;
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if (fsr & MA35_FSR_PEF)
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up->port.icount.parity++;
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if (fsr & MA35_FSR_RX_OVER_IF)
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up->port.icount.overrun++;
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serial_out(up, MA35_FSR_REG,
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fsr & (MA35_FSR_BIF | MA35_FSR_FEF |
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MA35_FSR_PEF | MA35_FSR_RX_OVER_IF));
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if (fsr & MA35_FSR_BIF)
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flag = TTY_BREAK;
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else if (fsr & MA35_FSR_PEF)
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flag = TTY_PARITY;
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else if (fsr & MA35_FSR_FEF)
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flag = TTY_FRAME;
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}
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ch = serial_in(up, MA35_RBR_REG);
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if (uart_handle_sysrq_char(&up->port, ch))
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continue;
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spin_lock(&up->port.lock);
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uart_insert_char(&up->port, fsr, MA35_FSR_RX_OVER_IF, ch, flag);
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spin_unlock(&up->port.lock);
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fsr = serial_in(up, MA35_FSR_REG);
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} while (!(fsr & MA35_FSR_RX_EMPTY) && (max_count-- > 0));
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spin_lock(&up->port.lock);
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tty_flip_buffer_push(&up->port.state->port);
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spin_unlock(&up->port.lock);
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}
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static irqreturn_t ma35d1serial_interrupt(int irq, void *dev_id)
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{
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struct uart_port *port = dev_id;
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struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
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u32 isr, fsr;
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isr = serial_in(up, MA35_ISR_REG);
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fsr = serial_in(up, MA35_FSR_REG);
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if (!(isr & MA35_ISR_IF_CHECK))
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return IRQ_NONE;
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if (isr & (MA35_ISR_RDA_IF | MA35_ISR_RXTO_IF))
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receive_chars(up);
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if (isr & MA35_ISR_THRE_INT)
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transmit_chars(up);
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if (fsr & MA35_FSR_TX_OVER_IF)
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serial_out(up, MA35_FSR_REG, MA35_FSR_TX_OVER_IF);
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return IRQ_HANDLED;
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}
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static u32 ma35d1serial_tx_empty(struct uart_port *port)
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{
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struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
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u32 fsr;
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fsr = serial_in(up, MA35_FSR_REG);
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if ((fsr & MA35_FSR_TX_BOTH_EMPTY) == MA35_FSR_TX_BOTH_EMPTY)
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return TIOCSER_TEMT;
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else
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return 0;
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}
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static u32 ma35d1serial_get_mctrl(struct uart_port *port)
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{
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struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
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u32 status;
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u32 ret = 0;
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status = serial_in(up, MA35_MSR_REG);
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if (!(status & MA35_MSR_CTSSTS))
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ret |= TIOCM_CTS;
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return ret;
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}
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static void ma35d1serial_set_mctrl(struct uart_port *port, u32 mctrl)
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{
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struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
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u32 mcr, msr, ier;
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mcr = serial_in(up, MA35_MCR_REG);
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mcr &= ~MA35_MCR_RTS_CTRL;
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if (mctrl & TIOCM_RTS)
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mcr |= MA35_MCR_RTSACTLV;
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else
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mcr &= ~MA35_MCR_RTSACTLV;
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if (up->mcr & UART_MCR_AFE) {
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ier = serial_in(up, MA35_IER_REG);
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ier |= MA35_IER_AUTO_RTS | MA35_IER_AUTO_CTS;
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serial_out(up, MA35_IER_REG, ier);
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up->port.flags |= UPF_HARD_FLOW;
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} else {
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ier = serial_in(up, MA35_IER_REG);
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ier &= ~(MA35_IER_AUTO_RTS | MA35_IER_AUTO_CTS);
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serial_out(up, MA35_IER_REG, ier);
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up->port.flags &= ~UPF_HARD_FLOW;
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}
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msr = serial_in(up, MA35_MSR_REG);
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msr |= MA35_MSR_CTSACTLV;
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serial_out(up, MA35_MSR_REG, msr);
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serial_out(up, MA35_MCR_REG, mcr);
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}
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static void ma35d1serial_break_ctl(struct uart_port *port, int break_state)
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{
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struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
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unsigned long flags;
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u32 lcr;
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spin_lock_irqsave(&up->port.lock, flags);
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lcr = serial_in(up, MA35_LCR_REG);
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if (break_state != 0)
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lcr |= MA35_LCR_BREAK;
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else
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lcr &= ~MA35_LCR_BREAK;
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serial_out(up, MA35_LCR_REG, lcr);
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spin_unlock_irqrestore(&up->port.lock, flags);
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}
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static int ma35d1serial_startup(struct uart_port *port)
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{
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struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
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u32 fcr;
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int retval;
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/* Reset FIFO */
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serial_out(up, MA35_FCR_REG, MA35_FCR_TFR | MA35_FCR_RFR);
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/* Clear pending interrupts */
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serial_out(up, MA35_ISR_REG, MA35_ISR_ALL);
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retval = request_irq(port->irq, ma35d1serial_interrupt, 0,
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dev_name(port->dev), port);
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if (retval) {
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dev_err(up->port.dev, "request irq failed.\n");
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return retval;
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}
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fcr = serial_in(up, MA35_FCR_REG);
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fcr |= MA35_FCR_RFITL_4BYTES | MA35_FCR_RTSTL_8BYTES;
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serial_out(up, MA35_FCR_REG, fcr);
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serial_out(up, MA35_LCR_REG, MA35_LCR_WLS_8BITS);
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serial_out(up, MA35_TOR_REG, MA35_UART_RX_TOUT);
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serial_out(up, MA35_IER_REG, MA35_IER_CONFIG);
|
|
return 0;
|
|
}
|
|
|
|
static void ma35d1serial_shutdown(struct uart_port *port)
|
|
{
|
|
struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
|
|
|
|
serial_out(up, MA35_IER_REG, 0);
|
|
free_irq(port->irq, port);
|
|
}
|
|
|
|
static void ma35d1serial_set_termios(struct uart_port *port,
|
|
struct ktermios *termios,
|
|
const struct ktermios *old)
|
|
{
|
|
struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
|
|
unsigned long flags;
|
|
u32 baud, quot;
|
|
u32 lcr = 0;
|
|
|
|
lcr = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
|
|
|
|
if (termios->c_cflag & CSTOPB)
|
|
lcr |= MA35_LCR_NSB;
|
|
if (termios->c_cflag & PARENB)
|
|
lcr |= MA35_LCR_PBE;
|
|
if (!(termios->c_cflag & PARODD))
|
|
lcr |= MA35_LCR_EPE;
|
|
if (termios->c_cflag & CMSPAR)
|
|
lcr |= MA35_LCR_SPE;
|
|
|
|
baud = uart_get_baud_rate(port, termios, old,
|
|
port->uartclk / MA35_BAUD_DIV_MAX,
|
|
port->uartclk / MA35_BAUD_DIV_MIN);
|
|
|
|
/* MA35D1 UART baud rate equation: baudrate = UART_CLK / (quot + 2) */
|
|
quot = (port->uartclk / baud) - 2;
|
|
|
|
/*
|
|
* Ok, we're now changing the port state. Do it with
|
|
* interrupts disabled.
|
|
*/
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
|
|
up->port.read_status_mask = MA35_FSR_RX_OVER_IF;
|
|
if (termios->c_iflag & INPCK)
|
|
up->port.read_status_mask |= MA35_FSR_FEF | MA35_FSR_PEF;
|
|
if (termios->c_iflag & (BRKINT | PARMRK))
|
|
up->port.read_status_mask |= MA35_FSR_BIF;
|
|
|
|
/* Characteres to ignore */
|
|
up->port.ignore_status_mask = 0;
|
|
if (termios->c_iflag & IGNPAR)
|
|
up->port.ignore_status_mask |= MA35_FSR_FEF | MA35_FSR_PEF;
|
|
if (termios->c_iflag & IGNBRK) {
|
|
up->port.ignore_status_mask |= MA35_FSR_BIF;
|
|
/*
|
|
* If we're ignoring parity and break indicators,
|
|
* ignore overruns too (for real raw support).
|
|
*/
|
|
if (termios->c_iflag & IGNPAR)
|
|
up->port.ignore_status_mask |= MA35_FSR_RX_OVER_IF;
|
|
}
|
|
if (termios->c_cflag & CRTSCTS)
|
|
up->mcr |= UART_MCR_AFE;
|
|
else
|
|
up->mcr &= ~UART_MCR_AFE;
|
|
|
|
uart_update_timeout(port, termios->c_cflag, baud);
|
|
|
|
ma35d1serial_set_mctrl(&up->port, up->port.mctrl);
|
|
|
|
serial_out(up, MA35_BAUD_REG, MA35_BAUD_MODE2 | FIELD_PREP(MA35_BAUD_MASK, quot));
|
|
|
|
serial_out(up, MA35_LCR_REG, lcr);
|
|
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
}
|
|
|
|
static const char *ma35d1serial_type(struct uart_port *port)
|
|
{
|
|
return "ma35d1-uart";
|
|
}
|
|
|
|
static void ma35d1serial_config_port(struct uart_port *port, int flags)
|
|
{
|
|
/*
|
|
* Driver core for serial ports forces a non-zero value for port type.
|
|
* Write an arbitrary value here to accommodate the serial core driver,
|
|
* as ID part of UAPI is redundant.
|
|
*/
|
|
port->type = 1;
|
|
}
|
|
|
|
static int ma35d1serial_verify_port(struct uart_port *port, struct serial_struct *ser)
|
|
{
|
|
if (port->type != PORT_UNKNOWN && ser->type != 1)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct uart_ops ma35d1serial_ops = {
|
|
.tx_empty = ma35d1serial_tx_empty,
|
|
.set_mctrl = ma35d1serial_set_mctrl,
|
|
.get_mctrl = ma35d1serial_get_mctrl,
|
|
.stop_tx = ma35d1serial_stop_tx,
|
|
.start_tx = ma35d1serial_start_tx,
|
|
.stop_rx = ma35d1serial_stop_rx,
|
|
.break_ctl = ma35d1serial_break_ctl,
|
|
.startup = ma35d1serial_startup,
|
|
.shutdown = ma35d1serial_shutdown,
|
|
.set_termios = ma35d1serial_set_termios,
|
|
.type = ma35d1serial_type,
|
|
.config_port = ma35d1serial_config_port,
|
|
.verify_port = ma35d1serial_verify_port,
|
|
};
|
|
|
|
static const struct of_device_id ma35d1_serial_of_match[] = {
|
|
{ .compatible = "nuvoton,ma35d1-uart" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ma35d1_serial_of_match);
|
|
|
|
#ifdef CONFIG_SERIAL_NUVOTON_MA35D1_CONSOLE
|
|
|
|
static struct device_node *ma35d1serial_uart_nodes[MA35_UART_NR];
|
|
|
|
static void wait_for_xmitr(struct uart_ma35d1_port *up)
|
|
{
|
|
unsigned int reg = 0;
|
|
|
|
read_poll_timeout_atomic(serial_in, reg, reg & MA35_FSR_TX_EMPTY,
|
|
1, 10000, false,
|
|
up, MA35_FSR_REG);
|
|
}
|
|
|
|
static void ma35d1serial_console_putchar(struct uart_port *port, unsigned char ch)
|
|
{
|
|
struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
|
|
|
|
wait_for_xmitr(up);
|
|
serial_out(up, MA35_THR_REG, ch);
|
|
}
|
|
|
|
/*
|
|
* Print a string to the serial port trying not to disturb
|
|
* any possible real use of the port...
|
|
*
|
|
* The console_lock must be held when we get here.
|
|
*/
|
|
static void ma35d1serial_console_write(struct console *co, const char *s, u32 count)
|
|
{
|
|
struct uart_ma35d1_port *up = &ma35d1serial_ports[co->index];
|
|
unsigned long flags;
|
|
int locked = 1;
|
|
u32 ier;
|
|
|
|
if (up->port.sysrq)
|
|
locked = 0;
|
|
else if (oops_in_progress)
|
|
locked = spin_trylock_irqsave(&up->port.lock, flags);
|
|
else
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
|
|
/*
|
|
* First save the IER then disable the interrupts
|
|
*/
|
|
ier = serial_in(up, MA35_IER_REG);
|
|
serial_out(up, MA35_IER_REG, 0);
|
|
|
|
uart_console_write(&up->port, s, count, ma35d1serial_console_putchar);
|
|
|
|
wait_for_xmitr(up);
|
|
serial_out(up, MA35_IER_REG, ier);
|
|
|
|
if (locked)
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
}
|
|
|
|
static int __init ma35d1serial_console_setup(struct console *co, char *options)
|
|
{
|
|
struct device_node *np;
|
|
struct uart_ma35d1_port *p;
|
|
u32 val32[4];
|
|
struct uart_port *port;
|
|
int baud = 115200;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
if ((co->index < 0) || (co->index >= MA35_UART_NR)) {
|
|
pr_debug("Console Port%x out of range\n", co->index);
|
|
return -EINVAL;
|
|
}
|
|
|
|
np = ma35d1serial_uart_nodes[co->index];
|
|
p = &ma35d1serial_ports[co->index];
|
|
if (!np || !p)
|
|
return -ENODEV;
|
|
|
|
if (of_property_read_u32_array(np, "reg", val32, ARRAY_SIZE(val32)) != 0)
|
|
return -EINVAL;
|
|
|
|
p->port.iobase = val32[1];
|
|
p->port.membase = ioremap(p->port.iobase, MA35_UART_REG_SIZE);
|
|
if (!p->port.membase)
|
|
return -ENOMEM;
|
|
|
|
p->port.ops = &ma35d1serial_ops;
|
|
p->port.line = 0;
|
|
p->port.uartclk = MA35_UART_CONSOLE_CLK;
|
|
|
|
port = &ma35d1serial_ports[co->index].port;
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
return uart_set_options(port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct console ma35d1serial_console = {
|
|
.name = "ttyNVT",
|
|
.write = ma35d1serial_console_write,
|
|
.device = uart_console_device,
|
|
.setup = ma35d1serial_console_setup,
|
|
.flags = CON_PRINTBUFFER | CON_ENABLED,
|
|
.index = -1,
|
|
.data = &ma35d1serial_reg,
|
|
};
|
|
|
|
static void ma35d1serial_console_init_port(void)
|
|
{
|
|
u32 i = 0;
|
|
struct device_node *np;
|
|
|
|
for_each_matching_node(np, ma35d1_serial_of_match) {
|
|
if (ma35d1serial_uart_nodes[i] == NULL) {
|
|
of_node_get(np);
|
|
ma35d1serial_uart_nodes[i] = np;
|
|
i++;
|
|
if (i == MA35_UART_NR)
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int __init ma35d1serial_console_init(void)
|
|
{
|
|
ma35d1serial_console_init_port();
|
|
register_console(&ma35d1serial_console);
|
|
return 0;
|
|
}
|
|
console_initcall(ma35d1serial_console_init);
|
|
|
|
#define MA35D1SERIAL_CONSOLE (&ma35d1serial_console)
|
|
#else
|
|
#define MA35D1SERIAL_CONSOLE NULL
|
|
#endif
|
|
|
|
static struct uart_driver ma35d1serial_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "serial",
|
|
.dev_name = "ttyNVT",
|
|
.major = TTY_MAJOR,
|
|
.minor = 64,
|
|
.cons = MA35D1SERIAL_CONSOLE,
|
|
.nr = MA35_UART_NR,
|
|
};
|
|
|
|
/*
|
|
* Register a set of serial devices attached to a platform device.
|
|
* The list is terminated with a zero flags entry, which means we expect
|
|
* all entries to have at least UPF_BOOT_AUTOCONF set.
|
|
*/
|
|
static int ma35d1serial_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res_mem;
|
|
struct uart_ma35d1_port *up;
|
|
int ret = 0;
|
|
|
|
if (pdev->dev.of_node) {
|
|
ret = of_alias_get_id(pdev->dev.of_node, "serial");
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
up = &ma35d1serial_ports[ret];
|
|
up->port.line = ret;
|
|
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res_mem)
|
|
return -ENODEV;
|
|
|
|
up->port.iobase = res_mem->start;
|
|
up->port.membase = ioremap(up->port.iobase, MA35_UART_REG_SIZE);
|
|
up->port.ops = &ma35d1serial_ops;
|
|
|
|
spin_lock_init(&up->port.lock);
|
|
|
|
up->clk = of_clk_get(pdev->dev.of_node, 0);
|
|
if (IS_ERR(up->clk)) {
|
|
ret = PTR_ERR(up->clk);
|
|
dev_err(&pdev->dev, "failed to get core clk: %d\n", ret);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
ret = clk_prepare_enable(up->clk);
|
|
if (ret)
|
|
goto err_iounmap;
|
|
|
|
if (up->port.line != 0)
|
|
up->port.uartclk = clk_get_rate(up->clk);
|
|
|
|
ret = platform_get_irq(pdev, 0);
|
|
if (ret < 0)
|
|
goto err_clk_disable;
|
|
|
|
up->port.irq = ret;
|
|
up->port.dev = &pdev->dev;
|
|
up->port.flags = UPF_BOOT_AUTOCONF;
|
|
|
|
platform_set_drvdata(pdev, up);
|
|
|
|
ret = uart_add_one_port(&ma35d1serial_reg, &up->port);
|
|
if (ret < 0)
|
|
goto err_free_irq;
|
|
|
|
return 0;
|
|
|
|
err_free_irq:
|
|
free_irq(up->port.irq, &up->port);
|
|
|
|
err_clk_disable:
|
|
clk_disable_unprepare(up->clk);
|
|
|
|
err_iounmap:
|
|
iounmap(up->port.membase);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Remove serial ports registered against a platform device.
|
|
*/
|
|
static int ma35d1serial_remove(struct platform_device *dev)
|
|
{
|
|
struct uart_port *port = platform_get_drvdata(dev);
|
|
struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
|
|
|
|
uart_remove_one_port(&ma35d1serial_reg, port);
|
|
clk_disable_unprepare(up->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int ma35d1serial_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct uart_port *port = platform_get_drvdata(dev);
|
|
struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
|
|
|
|
uart_suspend_port(&ma35d1serial_reg, &up->port);
|
|
if (up->port.line == 0) {
|
|
up->console_baud_rate = serial_in(up, MA35_BAUD_REG);
|
|
up->console_line = serial_in(up, MA35_LCR_REG);
|
|
up->console_int = serial_in(up, MA35_IER_REG);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int ma35d1serial_resume(struct platform_device *dev)
|
|
{
|
|
struct uart_port *port = platform_get_drvdata(dev);
|
|
struct uart_ma35d1_port *up = to_ma35d1_uart_port(port);
|
|
|
|
if (up->port.line == 0) {
|
|
serial_out(up, MA35_BAUD_REG, up->console_baud_rate);
|
|
serial_out(up, MA35_LCR_REG, up->console_line);
|
|
serial_out(up, MA35_IER_REG, up->console_int);
|
|
}
|
|
uart_resume_port(&ma35d1serial_reg, &up->port);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ma35d1serial_driver = {
|
|
.probe = ma35d1serial_probe,
|
|
.remove = ma35d1serial_remove,
|
|
.suspend = ma35d1serial_suspend,
|
|
.resume = ma35d1serial_resume,
|
|
.driver = {
|
|
.name = "ma35d1-uart",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = of_match_ptr(ma35d1_serial_of_match),
|
|
},
|
|
};
|
|
|
|
static int __init ma35d1serial_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = uart_register_driver(&ma35d1serial_reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&ma35d1serial_driver);
|
|
if (ret)
|
|
uart_unregister_driver(&ma35d1serial_reg);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit ma35d1serial_exit(void)
|
|
{
|
|
platform_driver_unregister(&ma35d1serial_driver);
|
|
uart_unregister_driver(&ma35d1serial_reg);
|
|
}
|
|
|
|
module_init(ma35d1serial_init);
|
|
module_exit(ma35d1serial_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("MA35D1 serial driver");
|