582 lines
15 KiB
C
582 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* linux/drivers/video/mmp/hw/mmp_ctrl.c
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* Marvell MMP series Display Controller support
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*
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* Copyright (C) 2012 Marvell Technology Group Ltd.
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* Authors: Guoqing Li <ligq@marvell.com>
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* Lisa Du <cldu@marvell.com>
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* Zhou Zhu <zzhu3@marvell.com>
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/vmalloc.h>
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#include <linux/uaccess.h>
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#include <linux/kthread.h>
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#include <linux/io.h>
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#include "mmp_ctrl.h"
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static irqreturn_t ctrl_handle_irq(int irq, void *dev_id)
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{
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struct mmphw_ctrl *ctrl = (struct mmphw_ctrl *)dev_id;
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u32 isr, imask, tmp;
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isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
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imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
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do {
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/* clear clock only */
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tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
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if (tmp & isr)
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writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);
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} while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask);
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return IRQ_HANDLED;
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}
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static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt)
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{
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u32 rbswap = 0, uvswap = 0, yuvswap = 0,
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csc_en = 0, val = 0,
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vid = overlay_is_vid(overlay);
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switch (pix_fmt) {
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case PIXFMT_RGB565:
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case PIXFMT_RGB1555:
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case PIXFMT_RGB888PACK:
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case PIXFMT_RGB888UNPACK:
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case PIXFMT_RGBA888:
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rbswap = 1;
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break;
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case PIXFMT_VYUY:
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case PIXFMT_YVU422P:
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case PIXFMT_YVU420P:
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uvswap = 1;
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break;
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case PIXFMT_YUYV:
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yuvswap = 1;
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break;
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default:
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break;
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}
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switch (pix_fmt) {
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case PIXFMT_RGB565:
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case PIXFMT_BGR565:
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break;
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case PIXFMT_RGB1555:
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case PIXFMT_BGR1555:
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val = 0x1;
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break;
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case PIXFMT_RGB888PACK:
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case PIXFMT_BGR888PACK:
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val = 0x2;
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break;
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case PIXFMT_RGB888UNPACK:
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case PIXFMT_BGR888UNPACK:
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val = 0x3;
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break;
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case PIXFMT_RGBA888:
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case PIXFMT_BGRA888:
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val = 0x4;
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break;
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case PIXFMT_UYVY:
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case PIXFMT_VYUY:
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case PIXFMT_YUYV:
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val = 0x5;
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csc_en = 1;
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break;
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case PIXFMT_YUV422P:
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case PIXFMT_YVU422P:
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val = 0x6;
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csc_en = 1;
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break;
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case PIXFMT_YUV420P:
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case PIXFMT_YVU420P:
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val = 0x7;
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csc_en = 1;
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break;
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default:
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break;
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}
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return (dma_palette(0) | dma_fmt(vid, val) |
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dma_swaprb(vid, rbswap) | dma_swapuv(vid, uvswap) |
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dma_swapyuv(vid, yuvswap) | dma_csc(vid, csc_en));
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}
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static void dmafetch_set_fmt(struct mmp_overlay *overlay)
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{
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u32 tmp;
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struct mmp_path *path = overlay->path;
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tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
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tmp &= ~dma_mask(overlay_is_vid(overlay));
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tmp |= fmt_to_reg(overlay, overlay->win.pix_fmt);
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writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
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}
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static void overlay_set_win(struct mmp_overlay *overlay, struct mmp_win *win)
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{
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struct lcd_regs *regs = path_regs(overlay->path);
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/* assert win supported */
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memcpy(&overlay->win, win, sizeof(struct mmp_win));
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mutex_lock(&overlay->access_ok);
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if (overlay_is_vid(overlay)) {
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writel_relaxed(win->pitch[0],
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(void __iomem *)®s->v_pitch_yc);
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writel_relaxed(win->pitch[2] << 16 | win->pitch[1],
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(void __iomem *)®s->v_pitch_uv);
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writel_relaxed((win->ysrc << 16) | win->xsrc,
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(void __iomem *)®s->v_size);
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writel_relaxed((win->ydst << 16) | win->xdst,
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(void __iomem *)®s->v_size_z);
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writel_relaxed(win->ypos << 16 | win->xpos,
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(void __iomem *)®s->v_start);
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} else {
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writel_relaxed(win->pitch[0], (void __iomem *)®s->g_pitch);
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writel_relaxed((win->ysrc << 16) | win->xsrc,
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(void __iomem *)®s->g_size);
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writel_relaxed((win->ydst << 16) | win->xdst,
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(void __iomem *)®s->g_size_z);
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writel_relaxed(win->ypos << 16 | win->xpos,
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(void __iomem *)®s->g_start);
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}
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dmafetch_set_fmt(overlay);
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mutex_unlock(&overlay->access_ok);
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}
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static void dmafetch_onoff(struct mmp_overlay *overlay, int on)
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{
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u32 mask = overlay_is_vid(overlay) ? CFG_DMA_ENA_MASK :
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CFG_GRA_ENA_MASK;
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u32 enable = overlay_is_vid(overlay) ? CFG_DMA_ENA(1) : CFG_GRA_ENA(1);
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u32 tmp;
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struct mmp_path *path = overlay->path;
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mutex_lock(&overlay->access_ok);
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tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
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tmp &= ~mask;
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tmp |= (on ? enable : 0);
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writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
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mutex_unlock(&overlay->access_ok);
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}
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static void path_enabledisable(struct mmp_path *path, int on)
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{
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u32 tmp;
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mutex_lock(&path->access_ok);
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tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
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if (on)
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tmp &= ~SCLK_DISABLE;
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else
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tmp |= SCLK_DISABLE;
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writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
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mutex_unlock(&path->access_ok);
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}
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static void path_onoff(struct mmp_path *path, int on)
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{
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if (path->status == on) {
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dev_info(path->dev, "path %s is already %s\n",
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path->name, stat_name(path->status));
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return;
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}
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if (on) {
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path_enabledisable(path, 1);
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if (path->panel && path->panel->set_onoff)
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path->panel->set_onoff(path->panel, 1);
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} else {
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if (path->panel && path->panel->set_onoff)
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path->panel->set_onoff(path->panel, 0);
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path_enabledisable(path, 0);
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}
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path->status = on;
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}
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static void overlay_set_onoff(struct mmp_overlay *overlay, int on)
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{
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if (overlay->status == on) {
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dev_info(overlay_to_ctrl(overlay)->dev, "overlay %s is already %s\n",
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overlay->path->name, stat_name(overlay->status));
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return;
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}
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overlay->status = on;
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dmafetch_onoff(overlay, on);
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if (overlay->path->ops.check_status(overlay->path)
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!= overlay->path->status)
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path_onoff(overlay->path, on);
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}
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static void overlay_set_fetch(struct mmp_overlay *overlay, int fetch_id)
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{
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overlay->dmafetch_id = fetch_id;
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}
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static int overlay_set_addr(struct mmp_overlay *overlay, struct mmp_addr *addr)
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{
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struct lcd_regs *regs = path_regs(overlay->path);
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/* FIXME: assert addr supported */
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memcpy(&overlay->addr, addr, sizeof(struct mmp_addr));
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if (overlay_is_vid(overlay)) {
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writel_relaxed(addr->phys[0], (void __iomem *)®s->v_y0);
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writel_relaxed(addr->phys[1], (void __iomem *)®s->v_u0);
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writel_relaxed(addr->phys[2], (void __iomem *)®s->v_v0);
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} else
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writel_relaxed(addr->phys[0], (void __iomem *)®s->g_0);
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return overlay->addr.phys[0];
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}
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static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode)
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{
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struct lcd_regs *regs = path_regs(path);
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u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div,
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link_config = path_to_path_plat(path)->link_config,
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dsi_rbswap = path_to_path_plat(path)->link_config;
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/* FIXME: assert videomode supported */
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memcpy(&path->mode, mode, sizeof(struct mmp_mode));
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mutex_lock(&path->access_ok);
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/* polarity of timing signals */
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tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;
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tmp |= mode->vsync_invert ? 0 : 0x8;
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tmp |= mode->hsync_invert ? 0 : 0x4;
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tmp |= link_config & CFG_DUMBMODE_MASK;
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tmp |= CFG_DUMB_ENA(1);
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writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));
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/* interface rb_swap setting */
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tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &
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(~(CFG_INTFRBSWAP_MASK));
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tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK;
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writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));
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writel_relaxed((mode->yres << 16) | mode->xres,
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(void __iomem *)®s->screen_active);
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writel_relaxed((mode->left_margin << 16) | mode->right_margin,
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(void __iomem *)®s->screen_h_porch);
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writel_relaxed((mode->upper_margin << 16) | mode->lower_margin,
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(void __iomem *)®s->screen_v_porch);
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total_x = mode->xres + mode->left_margin + mode->right_margin +
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mode->hsync_len;
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total_y = mode->yres + mode->upper_margin + mode->lower_margin +
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mode->vsync_len;
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writel_relaxed((total_y << 16) | total_x,
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(void __iomem *)®s->screen_size);
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/* vsync ctrl */
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if (path->output_type == PATH_OUT_DSI)
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vsync_ctrl = 0x01330133;
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else
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vsync_ctrl = ((mode->xres + mode->right_margin) << 16)
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| (mode->xres + mode->right_margin);
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writel_relaxed(vsync_ctrl, (void __iomem *)®s->vsync_ctrl);
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/* set pixclock div */
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sclk_src = clk_get_rate(path_to_ctrl(path)->clk);
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sclk_div = sclk_src / mode->pixclock_freq;
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if (sclk_div * mode->pixclock_freq < sclk_src)
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sclk_div++;
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dev_info(path->dev, "%s sclk_src %d sclk_div 0x%x pclk %d\n",
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__func__, sclk_src, sclk_div, mode->pixclock_freq);
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tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
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tmp &= ~CLK_INT_DIV_MASK;
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tmp |= sclk_div;
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writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
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mutex_unlock(&path->access_ok);
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}
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static struct mmp_overlay_ops mmphw_overlay_ops = {
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.set_fetch = overlay_set_fetch,
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.set_onoff = overlay_set_onoff,
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.set_win = overlay_set_win,
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.set_addr = overlay_set_addr,
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};
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static void ctrl_set_default(struct mmphw_ctrl *ctrl)
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{
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u32 tmp, irq_mask;
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/*
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* LCD Global control(LCD_TOP_CTRL) should be configed before
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* any other LCD registers read/write, or there maybe issues.
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*/
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tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL);
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tmp |= 0xfff0;
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writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);
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/* disable all interrupts */
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irq_mask = path_imasks(0) | err_imask(0) |
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path_imasks(1) | err_imask(1);
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tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
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tmp &= ~irq_mask;
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tmp |= irq_mask;
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writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);
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}
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static void path_set_default(struct mmp_path *path)
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{
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struct lcd_regs *regs = path_regs(path);
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u32 dma_ctrl1, mask, tmp, path_config;
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path_config = path_to_path_plat(path)->path_config;
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/* Configure IOPAD: should be parallel only */
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if (PATH_OUT_PARALLEL == path->output_type) {
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mask = CFG_IOPADMODE_MASK | CFG_BURST_MASK | CFG_BOUNDARY_MASK;
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tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL);
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tmp &= ~mask;
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tmp |= path_config;
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writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);
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}
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/* Select path clock source */
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tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
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tmp &= ~SCLK_SRC_SEL_MASK;
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tmp |= path_config;
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writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
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/*
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* Configure default bits: vsync triggers DMA,
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* power save enable, configure alpha registers to
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* display 100% graphics, and set pixel command.
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*/
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dma_ctrl1 = 0x2032ff81;
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dma_ctrl1 |= CFG_VSYNC_INV_MASK;
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writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));
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/* Configure default register values */
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writel_relaxed(0x00000000, (void __iomem *)®s->blank_color);
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writel_relaxed(0x00000000, (void __iomem *)®s->g_1);
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writel_relaxed(0x00000000, (void __iomem *)®s->g_start);
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/*
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* 1.enable multiple burst request in DMA AXI
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* bus arbiter for faster read if not tv path;
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* 2.enable horizontal smooth filter;
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*/
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mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | CFG_ARBFAST_ENA(1);
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tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
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tmp |= mask;
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if (PATH_TV == path->id)
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tmp &= ~CFG_ARBFAST_ENA(1);
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writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
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}
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static int path_init(struct mmphw_path_plat *path_plat,
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struct mmp_mach_path_config *config)
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{
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struct mmphw_ctrl *ctrl = path_plat->ctrl;
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struct mmp_path_info *path_info;
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struct mmp_path *path = NULL;
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dev_info(ctrl->dev, "%s: %s\n", __func__, config->name);
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/* init driver data */
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path_info = kzalloc(sizeof(*path_info), GFP_KERNEL);
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if (!path_info)
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return 0;
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path_info->name = config->name;
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path_info->id = path_plat->id;
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path_info->dev = ctrl->dev;
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path_info->overlay_num = config->overlay_num;
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path_info->overlay_ops = &mmphw_overlay_ops;
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path_info->set_mode = path_set_mode;
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path_info->plat_data = path_plat;
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/* create/register platform device */
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path = mmp_register_path(path_info);
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if (!path) {
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kfree(path_info);
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return 0;
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}
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path_plat->path = path;
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path_plat->path_config = config->path_config;
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path_plat->link_config = config->link_config;
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path_plat->dsi_rbswap = config->dsi_rbswap;
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path_set_default(path);
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kfree(path_info);
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return 1;
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}
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static void path_deinit(struct mmphw_path_plat *path_plat)
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{
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if (!path_plat)
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return;
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mmp_unregister_path(path_plat->path);
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}
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static int mmphw_probe(struct platform_device *pdev)
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{
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struct mmp_mach_plat_info *mi;
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struct resource *res;
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int ret, i, irq;
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struct mmphw_path_plat *path_plat;
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struct mmphw_ctrl *ctrl = NULL;
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/* get resources from platform data */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res == NULL) {
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dev_err(&pdev->dev, "%s: no IO memory defined\n", __func__);
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ret = -ENOENT;
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goto failed;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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ret = -ENOENT;
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goto failed;
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}
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/* get configs from platform data */
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mi = pdev->dev.platform_data;
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if (mi == NULL || !mi->path_num || !mi->paths) {
|
|
dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
|
|
ret = -EINVAL;
|
|
goto failed;
|
|
}
|
|
|
|
/* allocate */
|
|
ctrl = devm_kzalloc(&pdev->dev,
|
|
struct_size(ctrl, path_plats, mi->path_num),
|
|
GFP_KERNEL);
|
|
if (!ctrl) {
|
|
ret = -ENOMEM;
|
|
goto failed;
|
|
}
|
|
|
|
ctrl->name = mi->name;
|
|
ctrl->path_num = mi->path_num;
|
|
ctrl->dev = &pdev->dev;
|
|
ctrl->irq = irq;
|
|
platform_set_drvdata(pdev, ctrl);
|
|
mutex_init(&ctrl->access_ok);
|
|
|
|
/* map registers.*/
|
|
if (!devm_request_mem_region(ctrl->dev, res->start,
|
|
resource_size(res), ctrl->name)) {
|
|
dev_err(ctrl->dev,
|
|
"can't request region for resource %pR\n", res);
|
|
ret = -EINVAL;
|
|
goto failed;
|
|
}
|
|
|
|
ctrl->reg_base = devm_ioremap(ctrl->dev,
|
|
res->start, resource_size(res));
|
|
if (ctrl->reg_base == NULL) {
|
|
dev_err(ctrl->dev, "%s: res %pR map failed\n", __func__, res);
|
|
ret = -ENOMEM;
|
|
goto failed;
|
|
}
|
|
|
|
/* request irq */
|
|
ret = devm_request_irq(ctrl->dev, ctrl->irq, ctrl_handle_irq,
|
|
IRQF_SHARED, "lcd_controller", ctrl);
|
|
if (ret < 0) {
|
|
dev_err(ctrl->dev, "%s unable to request IRQ %d\n",
|
|
__func__, ctrl->irq);
|
|
ret = -ENXIO;
|
|
goto failed;
|
|
}
|
|
|
|
/* get clock */
|
|
ctrl->clk = devm_clk_get(ctrl->dev, mi->clk_name);
|
|
if (IS_ERR(ctrl->clk)) {
|
|
ret = PTR_ERR(ctrl->clk);
|
|
dev_err_probe(ctrl->dev, ret,
|
|
"unable to get clk %s\n", mi->clk_name);
|
|
goto failed;
|
|
}
|
|
ret = clk_prepare_enable(ctrl->clk);
|
|
if (ret)
|
|
goto failed;
|
|
|
|
/* init global regs */
|
|
ctrl_set_default(ctrl);
|
|
|
|
/* init pathes from machine info and register them */
|
|
for (i = 0; i < ctrl->path_num; i++) {
|
|
/* get from config and machine info */
|
|
path_plat = &ctrl->path_plats[i];
|
|
path_plat->id = i;
|
|
path_plat->ctrl = ctrl;
|
|
|
|
/* path init */
|
|
if (!path_init(path_plat, &mi->paths[i])) {
|
|
ret = -EINVAL;
|
|
goto failed_path_init;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_MMP_DISP_SPI
|
|
ret = lcd_spi_register(ctrl);
|
|
if (ret < 0)
|
|
goto failed_path_init;
|
|
#endif
|
|
|
|
dev_info(ctrl->dev, "device init done\n");
|
|
|
|
return 0;
|
|
|
|
failed_path_init:
|
|
for (i = 0; i < ctrl->path_num; i++) {
|
|
path_plat = &ctrl->path_plats[i];
|
|
path_deinit(path_plat);
|
|
}
|
|
|
|
clk_disable_unprepare(ctrl->clk);
|
|
failed:
|
|
dev_err(&pdev->dev, "device init failed\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver mmphw_driver = {
|
|
.driver = {
|
|
.name = "mmp-disp",
|
|
},
|
|
.probe = mmphw_probe,
|
|
};
|
|
|
|
static int mmphw_init(void)
|
|
{
|
|
return platform_driver_register(&mmphw_driver);
|
|
}
|
|
module_init(mmphw_init);
|
|
|
|
MODULE_AUTHOR("Li Guoqing<ligq@marvell.com>");
|
|
MODULE_DESCRIPTION("Framebuffer driver for mmp");
|
|
MODULE_LICENSE("GPL");
|