254 lines
5.4 KiB
C
254 lines
5.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
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/*
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* Copyright (C) 2023 Nuvoton Technologies.
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*/
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#ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H
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#define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H
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/* external and internal oscillator clocks */
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#define HXT 0
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#define HXT_GATE 1
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#define LXT 2
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#define LXT_GATE 3
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#define HIRC 4
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#define HIRC_GATE 5
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#define LIRC 6
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#define LIRC_GATE 7
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/* PLLs */
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#define CAPLL 8
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#define SYSPLL 9
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#define DDRPLL 10
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#define APLL 11
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#define EPLL 12
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#define VPLL 13
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/* EPLL divider */
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#define EPLL_DIV2 14
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#define EPLL_DIV4 15
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#define EPLL_DIV8 16
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/* CPU clock, system clock, AXI, HCLK and PCLK */
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#define CA35CLK_MUX 17
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#define AXICLK_DIV2 18
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#define AXICLK_DIV4 19
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#define AXICLK_MUX 20
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#define SYSCLK0_MUX 21
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#define SYSCLK1_MUX 22
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#define SYSCLK1_DIV2 23
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#define HCLK0 24
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#define HCLK1 25
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#define HCLK2 26
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#define PCLK0 27
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#define PCLK1 28
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#define PCLK2 29
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#define HCLK3 30
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#define PCLK3 31
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#define PCLK4 32
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/* AXI and AHB peripheral clocks */
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#define USBPHY0 33
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#define USBPHY1 34
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#define DDR0_GATE 35
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#define DDR6_GATE 36
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#define CAN0_MUX 37
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#define CAN0_DIV 38
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#define CAN0_GATE 39
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#define CAN1_MUX 40
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#define CAN1_DIV 41
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#define CAN1_GATE 42
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#define CAN2_MUX 43
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#define CAN2_DIV 44
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#define CAN2_GATE 45
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#define CAN3_MUX 46
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#define CAN3_DIV 47
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#define CAN3_GATE 48
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#define SDH0_MUX 49
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#define SDH0_GATE 50
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#define SDH1_MUX 51
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#define SDH1_GATE 52
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#define NAND_GATE 53
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#define USBD_GATE 54
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#define USBH_GATE 55
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#define HUSBH0_GATE 56
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#define HUSBH1_GATE 57
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#define GFX_MUX 58
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#define GFX_GATE 59
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#define VC8K_GATE 60
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#define DCU_MUX 61
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#define DCU_GATE 62
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#define DCUP_DIV 63
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#define EMAC0_GATE 64
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#define EMAC1_GATE 65
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#define CCAP0_MUX 66
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#define CCAP0_DIV 67
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#define CCAP0_GATE 68
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#define CCAP1_MUX 69
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#define CCAP1_DIV 70
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#define CCAP1_GATE 71
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#define PDMA0_GATE 72
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#define PDMA1_GATE 73
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#define PDMA2_GATE 74
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#define PDMA3_GATE 75
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#define WH0_GATE 76
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#define WH1_GATE 77
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#define HWS_GATE 78
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#define EBI_GATE 79
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#define SRAM0_GATE 80
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#define SRAM1_GATE 81
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#define ROM_GATE 82
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#define TRA_GATE 83
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#define DBG_MUX 84
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#define DBG_GATE 85
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#define CKO_MUX 86
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#define CKO_DIV 87
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#define CKO_GATE 88
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#define GTMR_GATE 89
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#define GPA_GATE 90
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#define GPB_GATE 91
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#define GPC_GATE 92
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#define GPD_GATE 93
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#define GPE_GATE 94
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#define GPF_GATE 95
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#define GPG_GATE 96
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#define GPH_GATE 97
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#define GPI_GATE 98
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#define GPJ_GATE 99
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#define GPK_GATE 100
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#define GPL_GATE 101
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#define GPM_GATE 102
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#define GPN_GATE 103
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/* APB peripheral clocks */
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#define TMR0_MUX 104
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#define TMR0_GATE 105
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#define TMR1_MUX 106
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#define TMR1_GATE 107
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#define TMR2_MUX 108
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#define TMR2_GATE 109
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#define TMR3_MUX 110
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#define TMR3_GATE 111
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#define TMR4_MUX 112
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#define TMR4_GATE 113
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#define TMR5_MUX 114
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#define TMR5_GATE 115
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#define TMR6_MUX 116
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#define TMR6_GATE 117
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#define TMR7_MUX 118
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#define TMR7_GATE 119
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#define TMR8_MUX 120
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#define TMR8_GATE 121
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#define TMR9_MUX 122
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#define TMR9_GATE 123
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#define TMR10_MUX 124
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#define TMR10_GATE 125
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#define TMR11_MUX 126
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#define TMR11_GATE 127
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#define UART0_MUX 128
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#define UART0_DIV 129
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#define UART0_GATE 130
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#define UART1_MUX 131
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#define UART1_DIV 132
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#define UART1_GATE 133
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#define UART2_MUX 134
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#define UART2_DIV 135
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#define UART2_GATE 136
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#define UART3_MUX 137
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#define UART3_DIV 138
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#define UART3_GATE 139
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#define UART4_MUX 140
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#define UART4_DIV 141
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#define UART4_GATE 142
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#define UART5_MUX 143
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#define UART5_DIV 144
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#define UART5_GATE 145
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#define UART6_MUX 146
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#define UART6_DIV 147
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#define UART6_GATE 148
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#define UART7_MUX 149
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#define UART7_DIV 150
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#define UART7_GATE 151
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#define UART8_MUX 152
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#define UART8_DIV 153
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#define UART8_GATE 154
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#define UART9_MUX 155
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#define UART9_DIV 156
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#define UART9_GATE 157
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#define UART10_MUX 158
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#define UART10_DIV 159
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#define UART10_GATE 160
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#define UART11_MUX 161
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#define UART11_DIV 162
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#define UART11_GATE 163
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#define UART12_MUX 164
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#define UART12_DIV 165
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#define UART12_GATE 166
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#define UART13_MUX 167
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#define UART13_DIV 168
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#define UART13_GATE 169
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#define UART14_MUX 170
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#define UART14_DIV 171
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#define UART14_GATE 172
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#define UART15_MUX 173
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#define UART15_DIV 174
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#define UART15_GATE 175
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#define UART16_MUX 176
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#define UART16_DIV 177
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#define UART16_GATE 178
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#define RTC_GATE 179
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#define DDR_GATE 180
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#define KPI_MUX 181
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#define KPI_DIV 182
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#define KPI_GATE 183
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#define I2C0_GATE 184
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#define I2C1_GATE 185
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#define I2C2_GATE 186
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#define I2C3_GATE 187
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#define I2C4_GATE 188
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#define I2C5_GATE 189
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#define QSPI0_MUX 190
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#define QSPI0_GATE 191
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#define QSPI1_MUX 192
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#define QSPI1_GATE 193
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#define SMC0_MUX 194
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#define SMC0_DIV 195
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#define SMC0_GATE 196
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#define SMC1_MUX 197
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#define SMC1_DIV 198
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#define SMC1_GATE 199
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#define WDT0_MUX 200
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#define WDT0_GATE 201
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#define WDT1_MUX 202
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#define WDT1_GATE 203
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#define WDT2_MUX 204
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#define WDT2_GATE 205
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#define WWDT0_MUX 206
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#define WWDT1_MUX 207
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#define WWDT2_MUX 208
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#define EPWM0_GATE 209
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#define EPWM1_GATE 210
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#define EPWM2_GATE 211
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#define I2S0_MUX 212
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#define I2S0_GATE 213
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#define I2S1_MUX 214
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#define I2S1_GATE 215
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#define SSMCC_GATE 216
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#define SSPCC_GATE 217
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#define SPI0_MUX 218
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#define SPI0_GATE 219
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#define SPI1_MUX 220
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#define SPI1_GATE 221
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#define SPI2_MUX 222
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#define SPI2_GATE 223
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#define SPI3_MUX 224
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#define SPI3_GATE 225
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#define ECAP0_GATE 226
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#define ECAP1_GATE 227
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#define ECAP2_GATE 228
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#define QEI0_GATE 229
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#define QEI1_GATE 230
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#define QEI2_GATE 231
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#define ADC_DIV 232
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#define ADC_GATE 233
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#define EADC_DIV 234
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#define EADC_GATE 235
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#define CLK_MAX_IDX 236
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#endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */
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