157 lines
3.9 KiB
C
157 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __MFD_MT6358_CORE_H__
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#define __MFD_MT6358_CORE_H__
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struct irq_top_t {
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int hwirq_base;
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unsigned int num_int_regs;
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unsigned int en_reg;
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unsigned int en_reg_shift;
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unsigned int sta_reg;
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unsigned int sta_reg_shift;
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unsigned int top_offset;
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};
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struct pmic_irq_data {
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unsigned int num_top;
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unsigned int num_pmic_irqs;
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unsigned short top_int_status_reg;
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bool *enable_hwirq;
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bool *cache_hwirq;
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const struct irq_top_t *pmic_ints;
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};
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enum mt6358_irq_top_status_shift {
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MT6358_BUCK_TOP = 0,
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MT6358_LDO_TOP,
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MT6358_PSC_TOP,
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MT6358_SCK_TOP,
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MT6358_BM_TOP,
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MT6358_HK_TOP,
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MT6358_AUD_TOP,
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MT6358_MISC_TOP,
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};
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enum mt6358_irq_numbers {
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MT6358_IRQ_VPROC11_OC = 0,
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MT6358_IRQ_VPROC12_OC,
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MT6358_IRQ_VCORE_OC,
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MT6358_IRQ_VGPU_OC,
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MT6358_IRQ_VMODEM_OC,
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MT6358_IRQ_VDRAM1_OC,
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MT6358_IRQ_VS1_OC,
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MT6358_IRQ_VS2_OC,
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MT6358_IRQ_VPA_OC,
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MT6358_IRQ_VCORE_PREOC,
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MT6358_IRQ_VFE28_OC = 16,
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MT6358_IRQ_VXO22_OC,
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MT6358_IRQ_VRF18_OC,
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MT6358_IRQ_VRF12_OC,
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MT6358_IRQ_VEFUSE_OC,
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MT6358_IRQ_VCN33_OC,
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MT6358_IRQ_VCN28_OC,
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MT6358_IRQ_VCN18_OC,
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MT6358_IRQ_VCAMA1_OC,
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MT6358_IRQ_VCAMA2_OC,
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MT6358_IRQ_VCAMD_OC,
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MT6358_IRQ_VCAMIO_OC,
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MT6358_IRQ_VLDO28_OC,
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MT6358_IRQ_VA12_OC,
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MT6358_IRQ_VAUX18_OC,
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MT6358_IRQ_VAUD28_OC,
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MT6358_IRQ_VIO28_OC,
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MT6358_IRQ_VIO18_OC,
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MT6358_IRQ_VSRAM_PROC11_OC,
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MT6358_IRQ_VSRAM_PROC12_OC,
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MT6358_IRQ_VSRAM_OTHERS_OC,
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MT6358_IRQ_VSRAM_GPU_OC,
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MT6358_IRQ_VDRAM2_OC,
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MT6358_IRQ_VMC_OC,
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MT6358_IRQ_VMCH_OC,
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MT6358_IRQ_VEMC_OC,
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MT6358_IRQ_VSIM1_OC,
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MT6358_IRQ_VSIM2_OC,
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MT6358_IRQ_VIBR_OC,
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MT6358_IRQ_VUSB_OC,
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MT6358_IRQ_VBIF28_OC,
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MT6358_IRQ_PWRKEY = 48,
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MT6358_IRQ_HOMEKEY,
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MT6358_IRQ_PWRKEY_R,
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MT6358_IRQ_HOMEKEY_R,
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MT6358_IRQ_NI_LBAT_INT,
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MT6358_IRQ_CHRDET,
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MT6358_IRQ_CHRDET_EDGE,
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MT6358_IRQ_VCDT_HV_DET,
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MT6358_IRQ_RTC = 64,
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MT6358_IRQ_FG_BAT0_H = 80,
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MT6358_IRQ_FG_BAT0_L,
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MT6358_IRQ_FG_CUR_H,
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MT6358_IRQ_FG_CUR_L,
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MT6358_IRQ_FG_ZCV,
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MT6358_IRQ_FG_BAT1_H,
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MT6358_IRQ_FG_BAT1_L,
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MT6358_IRQ_FG_N_CHARGE_L,
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MT6358_IRQ_FG_IAVG_H,
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MT6358_IRQ_FG_IAVG_L,
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MT6358_IRQ_FG_TIME_H,
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MT6358_IRQ_FG_DISCHARGE,
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MT6358_IRQ_FG_CHARGE,
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MT6358_IRQ_BATON_LV = 96,
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MT6358_IRQ_BATON_HT,
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MT6358_IRQ_BATON_BAT_IN,
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MT6358_IRQ_BATON_BAT_OUT,
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MT6358_IRQ_BIF,
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MT6358_IRQ_BAT_H = 112,
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MT6358_IRQ_BAT_L,
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MT6358_IRQ_BAT2_H,
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MT6358_IRQ_BAT2_L,
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MT6358_IRQ_BAT_TEMP_H,
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MT6358_IRQ_BAT_TEMP_L,
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MT6358_IRQ_AUXADC_IMP,
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MT6358_IRQ_NAG_C_DLTV,
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MT6358_IRQ_AUDIO = 128,
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MT6358_IRQ_ACCDET = 133,
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MT6358_IRQ_ACCDET_EINT0,
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MT6358_IRQ_ACCDET_EINT1,
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MT6358_IRQ_SPI_CMD_ALERT = 144,
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MT6358_IRQ_NR,
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};
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#define MT6358_IRQ_BUCK_BASE MT6358_IRQ_VPROC11_OC
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#define MT6358_IRQ_LDO_BASE MT6358_IRQ_VFE28_OC
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#define MT6358_IRQ_PSC_BASE MT6358_IRQ_PWRKEY
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#define MT6358_IRQ_SCK_BASE MT6358_IRQ_RTC
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#define MT6358_IRQ_BM_BASE MT6358_IRQ_FG_BAT0_H
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#define MT6358_IRQ_HK_BASE MT6358_IRQ_BAT_H
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#define MT6358_IRQ_AUD_BASE MT6358_IRQ_AUDIO
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#define MT6358_IRQ_MISC_BASE MT6358_IRQ_SPI_CMD_ALERT
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#define MT6358_IRQ_BUCK_BITS (MT6358_IRQ_VCORE_PREOC - MT6358_IRQ_BUCK_BASE + 1)
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#define MT6358_IRQ_LDO_BITS (MT6358_IRQ_VBIF28_OC - MT6358_IRQ_LDO_BASE + 1)
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#define MT6358_IRQ_PSC_BITS (MT6358_IRQ_VCDT_HV_DET - MT6358_IRQ_PSC_BASE + 1)
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#define MT6358_IRQ_SCK_BITS (MT6358_IRQ_RTC - MT6358_IRQ_SCK_BASE + 1)
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#define MT6358_IRQ_BM_BITS (MT6358_IRQ_BIF - MT6358_IRQ_BM_BASE + 1)
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#define MT6358_IRQ_HK_BITS (MT6358_IRQ_NAG_C_DLTV - MT6358_IRQ_HK_BASE + 1)
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#define MT6358_IRQ_AUD_BITS (MT6358_IRQ_ACCDET_EINT1 - MT6358_IRQ_AUD_BASE + 1)
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#define MT6358_IRQ_MISC_BITS \
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(MT6358_IRQ_SPI_CMD_ALERT - MT6358_IRQ_MISC_BASE + 1)
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#define MT6358_TOP_GEN(sp) \
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{ \
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.hwirq_base = MT6358_IRQ_##sp##_BASE, \
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.num_int_regs = \
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((MT6358_IRQ_##sp##_BITS - 1) / \
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MTK_PMIC_REG_WIDTH) + 1, \
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.en_reg = MT6358_##sp##_TOP_INT_CON0, \
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.en_reg_shift = 0x6, \
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.sta_reg = MT6358_##sp##_TOP_INT_STATUS0, \
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.sta_reg_shift = 0x2, \
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.top_offset = MT6358_##sp##_TOP, \
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}
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#endif /* __MFD_MT6358_CORE_H__ */
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