846 lines
17 KiB
C
846 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright (c) 2021, Microsoft Corporation. */
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#ifndef _GDMA_H
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#define _GDMA_H
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#include <linux/dma-mapping.h>
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#include <linux/netdevice.h>
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#include "shm_channel.h"
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#define GDMA_STATUS_MORE_ENTRIES 0x00000105
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/* Structures labeled with "HW DATA" are exchanged with the hardware. All of
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* them are naturally aligned and hence don't need __packed.
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*/
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enum gdma_request_type {
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GDMA_VERIFY_VF_DRIVER_VERSION = 1,
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GDMA_QUERY_MAX_RESOURCES = 2,
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GDMA_LIST_DEVICES = 3,
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GDMA_REGISTER_DEVICE = 4,
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GDMA_DEREGISTER_DEVICE = 5,
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GDMA_GENERATE_TEST_EQE = 10,
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GDMA_CREATE_QUEUE = 12,
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GDMA_DISABLE_QUEUE = 13,
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GDMA_ALLOCATE_RESOURCE_RANGE = 22,
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GDMA_DESTROY_RESOURCE_RANGE = 24,
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GDMA_CREATE_DMA_REGION = 25,
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GDMA_DMA_REGION_ADD_PAGES = 26,
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GDMA_DESTROY_DMA_REGION = 27,
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GDMA_CREATE_PD = 29,
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GDMA_DESTROY_PD = 30,
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GDMA_CREATE_MR = 31,
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GDMA_DESTROY_MR = 32,
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};
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#define GDMA_RESOURCE_DOORBELL_PAGE 27
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enum gdma_queue_type {
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GDMA_INVALID_QUEUE,
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GDMA_SQ,
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GDMA_RQ,
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GDMA_CQ,
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GDMA_EQ,
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};
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enum gdma_work_request_flags {
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GDMA_WR_NONE = 0,
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GDMA_WR_OOB_IN_SGL = BIT(0),
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GDMA_WR_PAD_BY_SGE0 = BIT(1),
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};
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enum gdma_eqe_type {
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GDMA_EQE_COMPLETION = 3,
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GDMA_EQE_TEST_EVENT = 64,
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GDMA_EQE_HWC_INIT_EQ_ID_DB = 129,
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GDMA_EQE_HWC_INIT_DATA = 130,
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GDMA_EQE_HWC_INIT_DONE = 131,
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};
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enum {
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GDMA_DEVICE_NONE = 0,
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GDMA_DEVICE_HWC = 1,
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GDMA_DEVICE_MANA = 2,
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};
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struct gdma_resource {
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/* Protect the bitmap */
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spinlock_t lock;
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/* The bitmap size in bits. */
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u32 size;
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/* The bitmap tracks the resources. */
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unsigned long *map;
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};
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union gdma_doorbell_entry {
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u64 as_uint64;
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struct {
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u64 id : 24;
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u64 reserved : 8;
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u64 tail_ptr : 31;
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u64 arm : 1;
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} cq;
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struct {
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u64 id : 24;
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u64 wqe_cnt : 8;
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u64 tail_ptr : 32;
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} rq;
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struct {
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u64 id : 24;
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u64 reserved : 8;
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u64 tail_ptr : 32;
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} sq;
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struct {
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u64 id : 16;
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u64 reserved : 16;
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u64 tail_ptr : 31;
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u64 arm : 1;
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} eq;
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}; /* HW DATA */
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struct gdma_msg_hdr {
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u32 hdr_type;
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u32 msg_type;
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u16 msg_version;
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u16 hwc_msg_id;
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u32 msg_size;
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}; /* HW DATA */
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struct gdma_dev_id {
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union {
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struct {
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u16 type;
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u16 instance;
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};
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u32 as_uint32;
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};
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}; /* HW DATA */
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struct gdma_req_hdr {
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struct gdma_msg_hdr req;
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struct gdma_msg_hdr resp; /* The expected response */
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struct gdma_dev_id dev_id;
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u32 activity_id;
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}; /* HW DATA */
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struct gdma_resp_hdr {
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struct gdma_msg_hdr response;
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struct gdma_dev_id dev_id;
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u32 activity_id;
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u32 status;
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u32 reserved;
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}; /* HW DATA */
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struct gdma_general_req {
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struct gdma_req_hdr hdr;
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}; /* HW DATA */
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#define GDMA_MESSAGE_V1 1
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#define GDMA_MESSAGE_V2 2
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struct gdma_general_resp {
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struct gdma_resp_hdr hdr;
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}; /* HW DATA */
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#define GDMA_STANDARD_HEADER_TYPE 0
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static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code,
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u32 req_size, u32 resp_size)
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{
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hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE;
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hdr->req.msg_type = code;
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hdr->req.msg_version = GDMA_MESSAGE_V1;
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hdr->req.msg_size = req_size;
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hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE;
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hdr->resp.msg_type = code;
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hdr->resp.msg_version = GDMA_MESSAGE_V1;
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hdr->resp.msg_size = resp_size;
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}
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/* The 16-byte struct is part of the GDMA work queue entry (WQE). */
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struct gdma_sge {
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u64 address;
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u32 mem_key;
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u32 size;
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}; /* HW DATA */
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struct gdma_wqe_request {
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struct gdma_sge *sgl;
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u32 num_sge;
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u32 inline_oob_size;
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const void *inline_oob_data;
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u32 flags;
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u32 client_data_unit;
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};
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enum gdma_page_type {
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GDMA_PAGE_TYPE_4K,
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};
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#define GDMA_INVALID_DMA_REGION 0
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struct gdma_mem_info {
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struct device *dev;
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dma_addr_t dma_handle;
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void *virt_addr;
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u64 length;
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/* Allocated by the PF driver */
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u64 dma_region_handle;
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};
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#define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8
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struct gdma_dev {
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struct gdma_context *gdma_context;
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struct gdma_dev_id dev_id;
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u32 pdid;
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u32 doorbell;
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u32 gpa_mkey;
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/* GDMA driver specific pointer */
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void *driver_data;
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struct auxiliary_device *adev;
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};
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#define MINIMUM_SUPPORTED_PAGE_SIZE PAGE_SIZE
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#define GDMA_CQE_SIZE 64
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#define GDMA_EQE_SIZE 16
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#define GDMA_MAX_SQE_SIZE 512
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#define GDMA_MAX_RQE_SIZE 256
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#define GDMA_COMP_DATA_SIZE 0x3C
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#define GDMA_EVENT_DATA_SIZE 0xC
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/* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */
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#define GDMA_WQE_BU_SIZE 32
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#define INVALID_PDID UINT_MAX
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#define INVALID_DOORBELL UINT_MAX
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#define INVALID_MEM_KEY UINT_MAX
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#define INVALID_QUEUE_ID UINT_MAX
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#define INVALID_PCI_MSIX_INDEX UINT_MAX
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struct gdma_comp {
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u32 cqe_data[GDMA_COMP_DATA_SIZE / 4];
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u32 wq_num;
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bool is_sq;
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};
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struct gdma_event {
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u32 details[GDMA_EVENT_DATA_SIZE / 4];
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u8 type;
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};
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struct gdma_queue;
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struct mana_eq {
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struct gdma_queue *eq;
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};
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typedef void gdma_eq_callback(void *context, struct gdma_queue *q,
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struct gdma_event *e);
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typedef void gdma_cq_callback(void *context, struct gdma_queue *q);
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/* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE
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* (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the
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* driver increases the 'head' in BUs rather than in bytes, and notifies
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* the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track
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* the HW head, and increases the 'head' by 1 for every processed EQE/CQE.
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*
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* The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is
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* processed, the driver increases the 'tail' to indicate that WQEs have
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* been consumed by the HW, so the driver can post new WQEs into the SQ/RQ.
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*
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* The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures
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* that the EQ/CQ is big enough so they can't overflow, and the driver uses
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* the owner bits mechanism to detect if the queue has become empty.
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*/
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struct gdma_queue {
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struct gdma_dev *gdma_dev;
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enum gdma_queue_type type;
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u32 id;
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struct gdma_mem_info mem_info;
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void *queue_mem_ptr;
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u32 queue_size;
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bool monitor_avl_buf;
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u32 head;
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u32 tail;
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/* Extra fields specific to EQ/CQ. */
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union {
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struct {
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bool disable_needed;
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gdma_eq_callback *callback;
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void *context;
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unsigned int msix_index;
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u32 log2_throttle_limit;
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} eq;
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struct {
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gdma_cq_callback *callback;
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void *context;
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struct gdma_queue *parent; /* For CQ/EQ relationship */
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} cq;
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};
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};
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struct gdma_queue_spec {
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enum gdma_queue_type type;
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bool monitor_avl_buf;
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unsigned int queue_size;
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/* Extra fields specific to EQ/CQ. */
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union {
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struct {
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gdma_eq_callback *callback;
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void *context;
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unsigned long log2_throttle_limit;
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} eq;
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struct {
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gdma_cq_callback *callback;
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void *context;
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struct gdma_queue *parent_eq;
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} cq;
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};
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};
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#define MANA_IRQ_NAME_SZ 32
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struct gdma_irq_context {
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void (*handler)(void *arg);
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void *arg;
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char name[MANA_IRQ_NAME_SZ];
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};
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struct gdma_context {
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struct device *dev;
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/* Per-vPort max number of queues */
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unsigned int max_num_queues;
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unsigned int max_num_msix;
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unsigned int num_msix_usable;
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struct gdma_resource msix_resource;
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struct gdma_irq_context *irq_contexts;
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/* L2 MTU */
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u16 adapter_mtu;
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/* This maps a CQ index to the queue structure. */
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unsigned int max_num_cqs;
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struct gdma_queue **cq_table;
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/* Protect eq_test_event and test_event_eq_id */
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struct mutex eq_test_event_mutex;
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struct completion eq_test_event;
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u32 test_event_eq_id;
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bool is_pf;
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phys_addr_t bar0_pa;
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void __iomem *bar0_va;
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void __iomem *shm_base;
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void __iomem *db_page_base;
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phys_addr_t phys_db_page_base;
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u32 db_page_size;
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int numa_node;
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/* Shared memory chanenl (used to bootstrap HWC) */
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struct shm_channel shm_channel;
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/* Hardware communication channel (HWC) */
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struct gdma_dev hwc;
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/* Azure network adapter */
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struct gdma_dev mana;
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};
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#define MAX_NUM_GDMA_DEVICES 4
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static inline bool mana_gd_is_mana(struct gdma_dev *gd)
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{
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return gd->dev_id.type == GDMA_DEVICE_MANA;
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}
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static inline bool mana_gd_is_hwc(struct gdma_dev *gd)
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{
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return gd->dev_id.type == GDMA_DEVICE_HWC;
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}
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u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset);
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u32 mana_gd_wq_avail_space(struct gdma_queue *wq);
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int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq);
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int mana_gd_create_hwc_queue(struct gdma_dev *gd,
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const struct gdma_queue_spec *spec,
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struct gdma_queue **queue_ptr);
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int mana_gd_create_mana_eq(struct gdma_dev *gd,
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const struct gdma_queue_spec *spec,
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struct gdma_queue **queue_ptr);
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int mana_gd_create_mana_wq_cq(struct gdma_dev *gd,
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const struct gdma_queue_spec *spec,
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struct gdma_queue **queue_ptr);
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void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue);
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int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe);
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void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit);
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struct gdma_wqe {
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u32 reserved :24;
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u32 last_vbytes :8;
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union {
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u32 flags;
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struct {
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u32 num_sge :8;
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u32 inline_oob_size_div4:3;
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u32 client_oob_in_sgl :1;
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u32 reserved1 :4;
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u32 client_data_unit :14;
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u32 reserved2 :2;
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};
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};
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}; /* HW DATA */
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#define INLINE_OOB_SMALL_SIZE 8
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#define INLINE_OOB_LARGE_SIZE 24
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#define MAX_TX_WQE_SIZE 512
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#define MAX_RX_WQE_SIZE 256
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#define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \
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sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \
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sizeof(struct gdma_sge))
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#define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \
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sizeof(struct gdma_sge)) / sizeof(struct gdma_sge))
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struct gdma_cqe {
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u32 cqe_data[GDMA_COMP_DATA_SIZE / 4];
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union {
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u32 as_uint32;
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struct {
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u32 wq_num : 24;
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u32 is_sq : 1;
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u32 reserved : 4;
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u32 owner_bits : 3;
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};
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} cqe_info;
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}; /* HW DATA */
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#define GDMA_CQE_OWNER_BITS 3
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#define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1)
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#define SET_ARM_BIT 1
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#define GDMA_EQE_OWNER_BITS 3
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union gdma_eqe_info {
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u32 as_uint32;
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struct {
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u32 type : 8;
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u32 reserved1 : 8;
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u32 client_id : 2;
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u32 reserved2 : 11;
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u32 owner_bits : 3;
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};
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}; /* HW DATA */
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#define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1)
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#define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries))
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struct gdma_eqe {
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u32 details[GDMA_EVENT_DATA_SIZE / 4];
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u32 eqe_info;
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}; /* HW DATA */
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#define GDMA_REG_DB_PAGE_OFFSET 8
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#define GDMA_REG_DB_PAGE_SIZE 0x10
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#define GDMA_REG_SHM_OFFSET 0x18
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#define GDMA_PF_REG_DB_PAGE_SIZE 0xD0
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#define GDMA_PF_REG_DB_PAGE_OFF 0xC8
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#define GDMA_PF_REG_SHM_OFF 0x70
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#define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108
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#define MANA_PF_DEVICE_ID 0x00B9
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#define MANA_VF_DEVICE_ID 0x00BA
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struct gdma_posted_wqe_info {
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u32 wqe_size_in_bu;
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};
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/* GDMA_GENERATE_TEST_EQE */
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struct gdma_generate_test_event_req {
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struct gdma_req_hdr hdr;
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u32 queue_index;
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}; /* HW DATA */
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/* GDMA_VERIFY_VF_DRIVER_VERSION */
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enum {
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GDMA_PROTOCOL_V1 = 1,
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GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1,
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GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1,
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};
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#define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0)
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/* Advertise to the NIC firmware: the NAPI work_done variable race is fixed,
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* so the driver is able to reliably support features like busy_poll.
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*/
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#define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2)
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#define GDMA_DRV_CAP_FLAGS1 \
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(GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \
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GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX)
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#define GDMA_DRV_CAP_FLAGS2 0
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#define GDMA_DRV_CAP_FLAGS3 0
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#define GDMA_DRV_CAP_FLAGS4 0
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struct gdma_verify_ver_req {
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struct gdma_req_hdr hdr;
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/* Mandatory fields required for protocol establishment */
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u64 protocol_ver_min;
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|
u64 protocol_ver_max;
|
|
|
|
/* Gdma Driver Capability Flags */
|
|
u64 gd_drv_cap_flags1;
|
|
u64 gd_drv_cap_flags2;
|
|
u64 gd_drv_cap_flags3;
|
|
u64 gd_drv_cap_flags4;
|
|
|
|
/* Advisory fields */
|
|
u64 drv_ver;
|
|
u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */
|
|
u32 reserved;
|
|
u32 os_ver_major;
|
|
u32 os_ver_minor;
|
|
u32 os_ver_build;
|
|
u32 os_ver_platform;
|
|
u64 reserved_2;
|
|
u8 os_ver_str1[128];
|
|
u8 os_ver_str2[128];
|
|
u8 os_ver_str3[128];
|
|
u8 os_ver_str4[128];
|
|
}; /* HW DATA */
|
|
|
|
struct gdma_verify_ver_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
u64 gdma_protocol_ver;
|
|
u64 pf_cap_flags1;
|
|
u64 pf_cap_flags2;
|
|
u64 pf_cap_flags3;
|
|
u64 pf_cap_flags4;
|
|
}; /* HW DATA */
|
|
|
|
/* GDMA_QUERY_MAX_RESOURCES */
|
|
struct gdma_query_max_resources_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
u32 status;
|
|
u32 max_sq;
|
|
u32 max_rq;
|
|
u32 max_cq;
|
|
u32 max_eq;
|
|
u32 max_db;
|
|
u32 max_mst;
|
|
u32 max_cq_mod_ctx;
|
|
u32 max_mod_cq;
|
|
u32 max_msix;
|
|
}; /* HW DATA */
|
|
|
|
/* GDMA_LIST_DEVICES */
|
|
struct gdma_list_devices_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
u32 num_of_devs;
|
|
u32 reserved;
|
|
struct gdma_dev_id devs[64];
|
|
}; /* HW DATA */
|
|
|
|
/* GDMA_REGISTER_DEVICE */
|
|
struct gdma_register_device_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
u32 pdid;
|
|
u32 gpa_mkey;
|
|
u32 db_id;
|
|
}; /* HW DATA */
|
|
|
|
struct gdma_allocate_resource_range_req {
|
|
struct gdma_req_hdr hdr;
|
|
u32 resource_type;
|
|
u32 num_resources;
|
|
u32 alignment;
|
|
u32 allocated_resources;
|
|
};
|
|
|
|
struct gdma_allocate_resource_range_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
u32 allocated_resources;
|
|
};
|
|
|
|
struct gdma_destroy_resource_range_req {
|
|
struct gdma_req_hdr hdr;
|
|
u32 resource_type;
|
|
u32 num_resources;
|
|
u32 allocated_resources;
|
|
};
|
|
|
|
/* GDMA_CREATE_QUEUE */
|
|
struct gdma_create_queue_req {
|
|
struct gdma_req_hdr hdr;
|
|
u32 type;
|
|
u32 reserved1;
|
|
u32 pdid;
|
|
u32 doolbell_id;
|
|
u64 gdma_region;
|
|
u32 reserved2;
|
|
u32 queue_size;
|
|
u32 log2_throttle_limit;
|
|
u32 eq_pci_msix_index;
|
|
u32 cq_mod_ctx_id;
|
|
u32 cq_parent_eq_id;
|
|
u8 rq_drop_on_overrun;
|
|
u8 rq_err_on_wqe_overflow;
|
|
u8 rq_chain_rec_wqes;
|
|
u8 sq_hw_db;
|
|
u32 reserved3;
|
|
}; /* HW DATA */
|
|
|
|
struct gdma_create_queue_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
u32 queue_index;
|
|
}; /* HW DATA */
|
|
|
|
/* GDMA_DISABLE_QUEUE */
|
|
struct gdma_disable_queue_req {
|
|
struct gdma_req_hdr hdr;
|
|
u32 type;
|
|
u32 queue_index;
|
|
u32 alloc_res_id_on_creation;
|
|
}; /* HW DATA */
|
|
|
|
enum atb_page_size {
|
|
ATB_PAGE_SIZE_4K,
|
|
ATB_PAGE_SIZE_8K,
|
|
ATB_PAGE_SIZE_16K,
|
|
ATB_PAGE_SIZE_32K,
|
|
ATB_PAGE_SIZE_64K,
|
|
ATB_PAGE_SIZE_128K,
|
|
ATB_PAGE_SIZE_256K,
|
|
ATB_PAGE_SIZE_512K,
|
|
ATB_PAGE_SIZE_1M,
|
|
ATB_PAGE_SIZE_2M,
|
|
ATB_PAGE_SIZE_MAX,
|
|
};
|
|
|
|
enum gdma_mr_access_flags {
|
|
GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0),
|
|
GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1),
|
|
GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2),
|
|
GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3),
|
|
GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4),
|
|
};
|
|
|
|
/* GDMA_CREATE_DMA_REGION */
|
|
struct gdma_create_dma_region_req {
|
|
struct gdma_req_hdr hdr;
|
|
|
|
/* The total size of the DMA region */
|
|
u64 length;
|
|
|
|
/* The offset in the first page */
|
|
u32 offset_in_page;
|
|
|
|
/* enum gdma_page_type */
|
|
u32 gdma_page_type;
|
|
|
|
/* The total number of pages */
|
|
u32 page_count;
|
|
|
|
/* If page_addr_list_len is smaller than page_count,
|
|
* the remaining page addresses will be added via the
|
|
* message GDMA_DMA_REGION_ADD_PAGES.
|
|
*/
|
|
u32 page_addr_list_len;
|
|
u64 page_addr_list[];
|
|
}; /* HW DATA */
|
|
|
|
struct gdma_create_dma_region_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
u64 dma_region_handle;
|
|
}; /* HW DATA */
|
|
|
|
/* GDMA_DMA_REGION_ADD_PAGES */
|
|
struct gdma_dma_region_add_pages_req {
|
|
struct gdma_req_hdr hdr;
|
|
|
|
u64 dma_region_handle;
|
|
|
|
u32 page_addr_list_len;
|
|
u32 reserved3;
|
|
|
|
u64 page_addr_list[];
|
|
}; /* HW DATA */
|
|
|
|
/* GDMA_DESTROY_DMA_REGION */
|
|
struct gdma_destroy_dma_region_req {
|
|
struct gdma_req_hdr hdr;
|
|
|
|
u64 dma_region_handle;
|
|
}; /* HW DATA */
|
|
|
|
enum gdma_pd_flags {
|
|
GDMA_PD_FLAG_INVALID = 0,
|
|
};
|
|
|
|
struct gdma_create_pd_req {
|
|
struct gdma_req_hdr hdr;
|
|
enum gdma_pd_flags flags;
|
|
u32 reserved;
|
|
};/* HW DATA */
|
|
|
|
struct gdma_create_pd_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
u64 pd_handle;
|
|
u32 pd_id;
|
|
u32 reserved;
|
|
};/* HW DATA */
|
|
|
|
struct gdma_destroy_pd_req {
|
|
struct gdma_req_hdr hdr;
|
|
u64 pd_handle;
|
|
};/* HW DATA */
|
|
|
|
struct gdma_destory_pd_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
};/* HW DATA */
|
|
|
|
enum gdma_mr_type {
|
|
/* Guest Virtual Address - MRs of this type allow access
|
|
* to memory mapped by PTEs associated with this MR using a virtual
|
|
* address that is set up in the MST
|
|
*/
|
|
GDMA_MR_TYPE_GVA = 2,
|
|
};
|
|
|
|
struct gdma_create_mr_params {
|
|
u64 pd_handle;
|
|
enum gdma_mr_type mr_type;
|
|
union {
|
|
struct {
|
|
u64 dma_region_handle;
|
|
u64 virtual_address;
|
|
enum gdma_mr_access_flags access_flags;
|
|
} gva;
|
|
};
|
|
};
|
|
|
|
struct gdma_create_mr_request {
|
|
struct gdma_req_hdr hdr;
|
|
u64 pd_handle;
|
|
enum gdma_mr_type mr_type;
|
|
u32 reserved_1;
|
|
|
|
union {
|
|
struct {
|
|
u64 dma_region_handle;
|
|
u64 virtual_address;
|
|
enum gdma_mr_access_flags access_flags;
|
|
} gva;
|
|
|
|
};
|
|
u32 reserved_2;
|
|
};/* HW DATA */
|
|
|
|
struct gdma_create_mr_response {
|
|
struct gdma_resp_hdr hdr;
|
|
u64 mr_handle;
|
|
u32 lkey;
|
|
u32 rkey;
|
|
};/* HW DATA */
|
|
|
|
struct gdma_destroy_mr_request {
|
|
struct gdma_req_hdr hdr;
|
|
u64 mr_handle;
|
|
};/* HW DATA */
|
|
|
|
struct gdma_destroy_mr_response {
|
|
struct gdma_resp_hdr hdr;
|
|
};/* HW DATA */
|
|
|
|
int mana_gd_verify_vf_version(struct pci_dev *pdev);
|
|
|
|
int mana_gd_register_device(struct gdma_dev *gd);
|
|
int mana_gd_deregister_device(struct gdma_dev *gd);
|
|
|
|
int mana_gd_post_work_request(struct gdma_queue *wq,
|
|
const struct gdma_wqe_request *wqe_req,
|
|
struct gdma_posted_wqe_info *wqe_info);
|
|
|
|
int mana_gd_post_and_ring(struct gdma_queue *queue,
|
|
const struct gdma_wqe_request *wqe,
|
|
struct gdma_posted_wqe_info *wqe_info);
|
|
|
|
int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r);
|
|
void mana_gd_free_res_map(struct gdma_resource *r);
|
|
|
|
void mana_gd_wq_ring_doorbell(struct gdma_context *gc,
|
|
struct gdma_queue *queue);
|
|
|
|
int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length,
|
|
struct gdma_mem_info *gmi);
|
|
|
|
void mana_gd_free_memory(struct gdma_mem_info *gmi);
|
|
|
|
int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req,
|
|
u32 resp_len, void *resp);
|
|
|
|
int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle);
|
|
|
|
#endif /* _GDMA_H */
|