568 lines
18 KiB
C
568 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* AMD ALSA SoC Pink Sardine SoundWire DMA Driver
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*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include <linux/pm_runtime.h>
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#include <linux/soundwire/sdw_amd.h>
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#include "acp63.h"
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#define DRV_NAME "amd_ps_sdw_dma"
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static struct sdw_dma_ring_buf_reg sdw0_dma_ring_buf_reg[ACP63_SDW0_DMA_MAX_STREAMS] = {
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{ACP_AUDIO0_TX_DMA_SIZE, ACP_AUDIO0_TX_FIFOADDR, ACP_AUDIO0_TX_FIFOSIZE,
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ACP_AUDIO0_TX_RINGBUFSIZE, ACP_AUDIO0_TX_RINGBUFADDR, ACP_AUDIO0_TX_INTR_WATERMARK_SIZE,
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ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH},
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{ACP_AUDIO1_TX_DMA_SIZE, ACP_AUDIO1_TX_FIFOADDR, ACP_AUDIO1_TX_FIFOSIZE,
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ACP_AUDIO1_TX_RINGBUFSIZE, ACP_AUDIO1_TX_RINGBUFADDR, ACP_AUDIO1_TX_INTR_WATERMARK_SIZE,
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ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH},
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{ACP_AUDIO2_TX_DMA_SIZE, ACP_AUDIO2_TX_FIFOADDR, ACP_AUDIO2_TX_FIFOSIZE,
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ACP_AUDIO2_TX_RINGBUFSIZE, ACP_AUDIO2_TX_RINGBUFADDR, ACP_AUDIO2_TX_INTR_WATERMARK_SIZE,
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ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH},
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{ACP_AUDIO0_RX_DMA_SIZE, ACP_AUDIO0_RX_FIFOADDR, ACP_AUDIO0_RX_FIFOSIZE,
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ACP_AUDIO0_RX_RINGBUFSIZE, ACP_AUDIO0_RX_RINGBUFADDR, ACP_AUDIO0_RX_INTR_WATERMARK_SIZE,
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ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH},
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{ACP_AUDIO1_RX_DMA_SIZE, ACP_AUDIO1_RX_FIFOADDR, ACP_AUDIO1_RX_FIFOSIZE,
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ACP_AUDIO1_RX_RINGBUFSIZE, ACP_AUDIO1_RX_RINGBUFADDR, ACP_AUDIO1_RX_INTR_WATERMARK_SIZE,
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ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH},
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{ACP_AUDIO2_RX_DMA_SIZE, ACP_AUDIO2_RX_FIFOADDR, ACP_AUDIO2_RX_FIFOSIZE,
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ACP_AUDIO2_RX_RINGBUFSIZE, ACP_AUDIO2_RX_RINGBUFADDR, ACP_AUDIO2_RX_INTR_WATERMARK_SIZE,
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ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH}
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};
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/*
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* SDW1 instance supports one TX stream and one RX stream.
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* For TX/RX streams DMA registers programming for SDW1 instance, it uses ACP_P1_AUDIO1 register
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* set as per hardware register documentation
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*/
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static struct sdw_dma_ring_buf_reg sdw1_dma_ring_buf_reg[ACP63_SDW1_DMA_MAX_STREAMS] = {
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{ACP_P1_AUDIO1_TX_DMA_SIZE, ACP_P1_AUDIO1_TX_FIFOADDR, ACP_P1_AUDIO1_TX_FIFOSIZE,
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ACP_P1_AUDIO1_TX_RINGBUFSIZE, ACP_P1_AUDIO1_TX_RINGBUFADDR,
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ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE,
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ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH},
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{ACP_P1_AUDIO1_RX_DMA_SIZE, ACP_P1_AUDIO1_RX_FIFOADDR, ACP_P1_AUDIO1_RX_FIFOSIZE,
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ACP_P1_AUDIO1_RX_RINGBUFSIZE, ACP_P1_AUDIO1_RX_RINGBUFADDR,
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ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE,
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ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH},
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};
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static u32 sdw0_dma_enable_reg[ACP63_SDW0_DMA_MAX_STREAMS] = {
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ACP_SW0_AUDIO0_TX_EN,
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ACP_SW0_AUDIO1_TX_EN,
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ACP_SW0_AUDIO2_TX_EN,
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ACP_SW0_AUDIO0_RX_EN,
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ACP_SW0_AUDIO1_RX_EN,
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ACP_SW0_AUDIO2_RX_EN,
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};
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/*
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* SDW1 instance supports one TX stream and one RX stream.
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* For TX/RX streams DMA enable register programming for SDW1 instance,
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* it uses ACP_SW1_AUDIO1_TX_EN and ACP_SW1_AUDIO1_RX_EN registers
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* as per hardware register documentation.
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*/
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static u32 sdw1_dma_enable_reg[ACP63_SDW1_DMA_MAX_STREAMS] = {
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ACP_SW1_AUDIO1_TX_EN,
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ACP_SW1_AUDIO1_RX_EN,
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};
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static const struct snd_pcm_hardware acp63_sdw_hardware_playback = {
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.info = SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_BLOCK_TRANSFER |
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SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_48000,
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.rate_min = 48000,
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.rate_max = 48000,
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.buffer_bytes_max = SDW_PLAYBACK_MAX_NUM_PERIODS * SDW_PLAYBACK_MAX_PERIOD_SIZE,
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.period_bytes_min = SDW_PLAYBACK_MIN_PERIOD_SIZE,
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.period_bytes_max = SDW_PLAYBACK_MAX_PERIOD_SIZE,
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.periods_min = SDW_PLAYBACK_MIN_NUM_PERIODS,
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.periods_max = SDW_PLAYBACK_MAX_NUM_PERIODS,
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};
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static const struct snd_pcm_hardware acp63_sdw_hardware_capture = {
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.info = SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_BLOCK_TRANSFER |
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SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_48000,
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.rate_min = 48000,
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.rate_max = 48000,
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.buffer_bytes_max = SDW_CAPTURE_MAX_NUM_PERIODS * SDW_CAPTURE_MAX_PERIOD_SIZE,
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.period_bytes_min = SDW_CAPTURE_MIN_PERIOD_SIZE,
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.period_bytes_max = SDW_CAPTURE_MAX_PERIOD_SIZE,
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.periods_min = SDW_CAPTURE_MIN_NUM_PERIODS,
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.periods_max = SDW_CAPTURE_MAX_NUM_PERIODS,
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};
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static void acp63_enable_disable_sdw_dma_interrupts(void __iomem *acp_base, bool enable)
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{
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u32 ext_intr_cntl, ext_intr_cntl1;
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u32 irq_mask = ACP_SDW_DMA_IRQ_MASK;
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u32 irq_mask1 = ACP_P1_SDW_DMA_IRQ_MASK;
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if (enable) {
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ext_intr_cntl = readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
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ext_intr_cntl |= irq_mask;
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writel(ext_intr_cntl, acp_base + ACP_EXTERNAL_INTR_CNTL);
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ext_intr_cntl1 = readl(acp_base + ACP_EXTERNAL_INTR_CNTL1);
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ext_intr_cntl1 |= irq_mask1;
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writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1);
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} else {
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ext_intr_cntl = readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
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ext_intr_cntl &= ~irq_mask;
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writel(ext_intr_cntl, acp_base + ACP_EXTERNAL_INTR_CNTL);
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ext_intr_cntl1 = readl(acp_base + ACP_EXTERNAL_INTR_CNTL1);
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ext_intr_cntl1 &= ~irq_mask1;
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writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1);
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}
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}
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static void acp63_config_dma(struct acp_sdw_dma_stream *stream, void __iomem *acp_base,
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u32 stream_id)
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{
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u16 page_idx;
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u32 low, high, val;
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u32 sdw_dma_pte_offset;
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dma_addr_t addr;
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addr = stream->dma_addr;
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sdw_dma_pte_offset = SDW_PTE_OFFSET(stream->instance);
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val = sdw_dma_pte_offset + (stream_id * ACP_SDW_PTE_OFFSET);
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/* Group Enable */
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writel(ACP_SDW_SRAM_PTE_OFFSET | BIT(31), acp_base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_2);
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writel(PAGE_SIZE_4K_ENABLE, acp_base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2);
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for (page_idx = 0; page_idx < stream->num_pages; page_idx++) {
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/* Load the low address of page int ACP SRAM through SRBM */
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low = lower_32_bits(addr);
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high = upper_32_bits(addr);
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writel(low, acp_base + ACP_SCRATCH_REG_0 + val);
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high |= BIT(31);
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writel(high, acp_base + ACP_SCRATCH_REG_0 + val + 4);
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val += 8;
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addr += PAGE_SIZE;
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}
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writel(0x1, acp_base + ACPAXI2AXI_ATU_CTRL);
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}
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static int acp63_configure_sdw_ringbuffer(void __iomem *acp_base, u32 stream_id, u32 size,
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u32 manager_instance)
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{
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u32 reg_dma_size;
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u32 reg_fifo_addr;
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u32 reg_fifo_size;
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u32 reg_ring_buf_size;
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u32 reg_ring_buf_addr;
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u32 sdw_fifo_addr;
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u32 sdw_fifo_offset;
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u32 sdw_ring_buf_addr;
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u32 sdw_ring_buf_size;
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u32 sdw_mem_window_offset;
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switch (manager_instance) {
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case ACP_SDW0:
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reg_dma_size = sdw0_dma_ring_buf_reg[stream_id].reg_dma_size;
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reg_fifo_addr = sdw0_dma_ring_buf_reg[stream_id].reg_fifo_addr;
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reg_fifo_size = sdw0_dma_ring_buf_reg[stream_id].reg_fifo_size;
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reg_ring_buf_size = sdw0_dma_ring_buf_reg[stream_id].reg_ring_buf_size;
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reg_ring_buf_addr = sdw0_dma_ring_buf_reg[stream_id].reg_ring_buf_addr;
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break;
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case ACP_SDW1:
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reg_dma_size = sdw1_dma_ring_buf_reg[stream_id].reg_dma_size;
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reg_fifo_addr = sdw1_dma_ring_buf_reg[stream_id].reg_fifo_addr;
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reg_fifo_size = sdw1_dma_ring_buf_reg[stream_id].reg_fifo_size;
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reg_ring_buf_size = sdw1_dma_ring_buf_reg[stream_id].reg_ring_buf_size;
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reg_ring_buf_addr = sdw1_dma_ring_buf_reg[stream_id].reg_ring_buf_addr;
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break;
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default:
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return -EINVAL;
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}
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sdw_fifo_offset = ACP_SDW_FIFO_OFFSET(manager_instance);
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sdw_mem_window_offset = SDW_MEM_WINDOW_START(manager_instance);
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sdw_fifo_addr = sdw_fifo_offset + (stream_id * SDW_FIFO_OFFSET);
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sdw_ring_buf_addr = sdw_mem_window_offset + (stream_id * ACP_SDW_RING_BUFF_ADDR_OFFSET);
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sdw_ring_buf_size = size;
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writel(sdw_ring_buf_size, acp_base + reg_ring_buf_size);
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writel(sdw_ring_buf_addr, acp_base + reg_ring_buf_addr);
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writel(sdw_fifo_addr, acp_base + reg_fifo_addr);
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writel(SDW_DMA_SIZE, acp_base + reg_dma_size);
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writel(SDW_FIFO_SIZE, acp_base + reg_fifo_size);
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return 0;
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}
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static int acp63_sdw_dma_open(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime;
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struct acp_sdw_dma_stream *stream;
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struct snd_soc_dai *cpu_dai;
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struct amd_sdw_manager *amd_manager;
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struct snd_soc_pcm_runtime *prtd = substream->private_data;
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int ret;
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runtime = substream->runtime;
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cpu_dai = asoc_rtd_to_cpu(prtd, 0);
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amd_manager = snd_soc_dai_get_drvdata(cpu_dai);
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stream = kzalloc(sizeof(*stream), GFP_KERNEL);
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if (!stream)
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return -ENOMEM;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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runtime->hw = acp63_sdw_hardware_playback;
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else
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runtime->hw = acp63_sdw_hardware_capture;
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ret = snd_pcm_hw_constraint_integer(runtime,
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SNDRV_PCM_HW_PARAM_PERIODS);
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if (ret < 0) {
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dev_err(component->dev, "set integer constraint failed\n");
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kfree(stream);
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return ret;
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}
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stream->stream_id = cpu_dai->id;
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stream->instance = amd_manager->instance;
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runtime->private_data = stream;
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return ret;
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}
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static int acp63_sdw_dma_hw_params(struct snd_soc_component *component,
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struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct acp_sdw_dma_stream *stream;
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struct sdw_dma_dev_data *sdw_data;
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u32 period_bytes;
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u32 water_mark_size_reg;
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u32 irq_mask, ext_intr_ctrl;
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u64 size;
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u32 stream_id;
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u32 acp_ext_intr_cntl_reg;
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int ret;
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sdw_data = dev_get_drvdata(component->dev);
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stream = substream->runtime->private_data;
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if (!stream)
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return -EINVAL;
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stream_id = stream->stream_id;
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switch (stream->instance) {
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case ACP_SDW0:
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sdw_data->sdw0_dma_stream[stream_id] = substream;
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water_mark_size_reg = sdw0_dma_ring_buf_reg[stream_id].water_mark_size_reg;
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acp_ext_intr_cntl_reg = ACP_EXTERNAL_INTR_CNTL;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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irq_mask = BIT(SDW0_DMA_TX_IRQ_MASK(stream_id));
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else
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irq_mask = BIT(SDW0_DMA_RX_IRQ_MASK(stream_id));
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break;
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case ACP_SDW1:
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sdw_data->sdw1_dma_stream[stream_id] = substream;
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acp_ext_intr_cntl_reg = ACP_EXTERNAL_INTR_CNTL1;
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water_mark_size_reg = sdw1_dma_ring_buf_reg[stream_id].water_mark_size_reg;
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irq_mask = BIT(SDW1_DMA_IRQ_MASK(stream_id));
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break;
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default:
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return -EINVAL;
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}
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size = params_buffer_bytes(params);
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period_bytes = params_period_bytes(params);
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stream->dma_addr = substream->runtime->dma_addr;
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stream->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
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acp63_config_dma(stream, sdw_data->acp_base, stream_id);
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ret = acp63_configure_sdw_ringbuffer(sdw_data->acp_base, stream_id, size,
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stream->instance);
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if (ret) {
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dev_err(component->dev, "Invalid DMA channel\n");
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return -EINVAL;
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}
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ext_intr_ctrl = readl(sdw_data->acp_base + acp_ext_intr_cntl_reg);
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ext_intr_ctrl |= irq_mask;
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writel(ext_intr_ctrl, sdw_data->acp_base + acp_ext_intr_cntl_reg);
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writel(period_bytes, sdw_data->acp_base + water_mark_size_reg);
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return 0;
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}
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static u64 acp63_sdw_get_byte_count(struct acp_sdw_dma_stream *stream, void __iomem *acp_base)
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{
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union acp_sdw_dma_count byte_count;
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u32 pos_low_reg, pos_high_reg;
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byte_count.bytescount = 0;
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switch (stream->instance) {
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case ACP_SDW0:
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pos_low_reg = sdw0_dma_ring_buf_reg[stream->stream_id].pos_low_reg;
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pos_high_reg = sdw0_dma_ring_buf_reg[stream->stream_id].pos_high_reg;
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break;
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case ACP_SDW1:
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pos_low_reg = sdw1_dma_ring_buf_reg[stream->stream_id].pos_low_reg;
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pos_high_reg = sdw1_dma_ring_buf_reg[stream->stream_id].pos_high_reg;
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break;
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default:
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goto POINTER_RETURN_BYTES;
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}
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if (pos_low_reg) {
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byte_count.bcount.high = readl(acp_base + pos_high_reg);
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byte_count.bcount.low = readl(acp_base + pos_low_reg);
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}
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POINTER_RETURN_BYTES:
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return byte_count.bytescount;
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}
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static snd_pcm_uframes_t acp63_sdw_dma_pointer(struct snd_soc_component *comp,
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struct snd_pcm_substream *substream)
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{
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struct sdw_dma_dev_data *sdw_data;
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struct acp_sdw_dma_stream *stream;
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u32 pos, buffersize;
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u64 bytescount;
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sdw_data = dev_get_drvdata(comp->dev);
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stream = substream->runtime->private_data;
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buffersize = frames_to_bytes(substream->runtime,
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substream->runtime->buffer_size);
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bytescount = acp63_sdw_get_byte_count(stream, sdw_data->acp_base);
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if (bytescount > stream->bytescount)
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bytescount -= stream->bytescount;
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pos = do_div(bytescount, buffersize);
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return bytes_to_frames(substream->runtime, pos);
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}
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static int acp63_sdw_dma_new(struct snd_soc_component *component,
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struct snd_soc_pcm_runtime *rtd)
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{
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struct device *parent = component->dev->parent;
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snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
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parent, SDW_MIN_BUFFER, SDW_MAX_BUFFER);
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return 0;
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}
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static int acp63_sdw_dma_close(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct sdw_dma_dev_data *sdw_data;
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struct acp_sdw_dma_stream *stream;
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sdw_data = dev_get_drvdata(component->dev);
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stream = substream->runtime->private_data;
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|
if (!stream)
|
|
return -EINVAL;
|
|
switch (stream->instance) {
|
|
case ACP_SDW0:
|
|
sdw_data->sdw0_dma_stream[stream->stream_id] = NULL;
|
|
break;
|
|
case ACP_SDW1:
|
|
sdw_data->sdw1_dma_stream[stream->stream_id] = NULL;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
kfree(stream);
|
|
return 0;
|
|
}
|
|
|
|
static int acp63_sdw_dma_enable(struct snd_pcm_substream *substream,
|
|
void __iomem *acp_base, bool sdw_dma_enable)
|
|
{
|
|
struct acp_sdw_dma_stream *stream;
|
|
u32 stream_id;
|
|
u32 sdw_dma_en_reg;
|
|
u32 sdw_dma_en_stat_reg;
|
|
u32 sdw_dma_stat;
|
|
u32 dma_enable;
|
|
|
|
stream = substream->runtime->private_data;
|
|
stream_id = stream->stream_id;
|
|
switch (stream->instance) {
|
|
case ACP_SDW0:
|
|
sdw_dma_en_reg = sdw0_dma_enable_reg[stream_id];
|
|
break;
|
|
case ACP_SDW1:
|
|
sdw_dma_en_reg = sdw1_dma_enable_reg[stream_id];
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
sdw_dma_en_stat_reg = sdw_dma_en_reg + 4;
|
|
dma_enable = sdw_dma_enable;
|
|
writel(dma_enable, acp_base + sdw_dma_en_reg);
|
|
return readl_poll_timeout(acp_base + sdw_dma_en_stat_reg, sdw_dma_stat,
|
|
(sdw_dma_stat == dma_enable), ACP_DELAY_US, ACP_COUNTER);
|
|
}
|
|
|
|
static int acp63_sdw_dma_trigger(struct snd_soc_component *comp,
|
|
struct snd_pcm_substream *substream,
|
|
int cmd)
|
|
{
|
|
struct sdw_dma_dev_data *sdw_data;
|
|
int ret;
|
|
|
|
sdw_data = dev_get_drvdata(comp->dev);
|
|
switch (cmd) {
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
ret = acp63_sdw_dma_enable(substream, sdw_data->acp_base, true);
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
ret = acp63_sdw_dma_enable(substream, sdw_data->acp_base, false);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
if (ret)
|
|
dev_err(comp->dev, "trigger %d failed: %d", cmd, ret);
|
|
return ret;
|
|
}
|
|
|
|
static const struct snd_soc_component_driver acp63_sdw_component = {
|
|
.name = DRV_NAME,
|
|
.open = acp63_sdw_dma_open,
|
|
.close = acp63_sdw_dma_close,
|
|
.hw_params = acp63_sdw_dma_hw_params,
|
|
.trigger = acp63_sdw_dma_trigger,
|
|
.pointer = acp63_sdw_dma_pointer,
|
|
.pcm_construct = acp63_sdw_dma_new,
|
|
};
|
|
|
|
static int acp63_sdw_platform_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
struct sdw_dma_dev_data *sdw_data;
|
|
struct acp63_dev_data *acp_data;
|
|
struct device *parent;
|
|
int status;
|
|
|
|
parent = pdev->dev.parent;
|
|
acp_data = dev_get_drvdata(parent);
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
sdw_data = devm_kzalloc(&pdev->dev, sizeof(*sdw_data), GFP_KERNEL);
|
|
if (!sdw_data)
|
|
return -ENOMEM;
|
|
|
|
sdw_data->acp_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
|
|
if (!sdw_data->acp_base)
|
|
return -ENOMEM;
|
|
|
|
sdw_data->acp_lock = &acp_data->acp_lock;
|
|
dev_set_drvdata(&pdev->dev, sdw_data);
|
|
status = devm_snd_soc_register_component(&pdev->dev,
|
|
&acp63_sdw_component,
|
|
NULL, 0);
|
|
if (status) {
|
|
dev_err(&pdev->dev, "Fail to register sdw dma component\n");
|
|
return status;
|
|
}
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS);
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_runtime_mark_last_busy(&pdev->dev);
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static int acp63_sdw_platform_remove(struct platform_device *pdev)
|
|
{
|
|
pm_runtime_disable(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static int acp_restore_sdw_dma_config(struct sdw_dma_dev_data *sdw_data)
|
|
{
|
|
struct acp_sdw_dma_stream *stream;
|
|
struct snd_pcm_substream *substream;
|
|
struct snd_pcm_runtime *runtime;
|
|
u32 period_bytes, buf_size, water_mark_size_reg;
|
|
u32 stream_count;
|
|
int index, instance, ret;
|
|
|
|
for (instance = 0; instance < AMD_SDW_MAX_MANAGERS; instance++) {
|
|
if (instance == ACP_SDW0)
|
|
stream_count = ACP63_SDW0_DMA_MAX_STREAMS;
|
|
else
|
|
stream_count = ACP63_SDW1_DMA_MAX_STREAMS;
|
|
|
|
for (index = 0; index < stream_count; index++) {
|
|
if (instance == ACP_SDW0) {
|
|
substream = sdw_data->sdw0_dma_stream[index];
|
|
water_mark_size_reg =
|
|
sdw0_dma_ring_buf_reg[index].water_mark_size_reg;
|
|
} else {
|
|
substream = sdw_data->sdw1_dma_stream[index];
|
|
water_mark_size_reg =
|
|
sdw1_dma_ring_buf_reg[index].water_mark_size_reg;
|
|
}
|
|
|
|
if (substream && substream->runtime) {
|
|
runtime = substream->runtime;
|
|
stream = runtime->private_data;
|
|
period_bytes = frames_to_bytes(runtime, runtime->period_size);
|
|
buf_size = frames_to_bytes(runtime, runtime->buffer_size);
|
|
acp63_config_dma(stream, sdw_data->acp_base, index);
|
|
ret = acp63_configure_sdw_ringbuffer(sdw_data->acp_base, index,
|
|
buf_size, instance);
|
|
if (ret)
|
|
return ret;
|
|
writel(period_bytes, sdw_data->acp_base + water_mark_size_reg);
|
|
}
|
|
}
|
|
}
|
|
acp63_enable_disable_sdw_dma_interrupts(sdw_data->acp_base, true);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused acp63_sdw_pcm_resume(struct device *dev)
|
|
{
|
|
struct sdw_dma_dev_data *sdw_data;
|
|
|
|
sdw_data = dev_get_drvdata(dev);
|
|
return acp_restore_sdw_dma_config(sdw_data);
|
|
}
|
|
|
|
static const struct dev_pm_ops acp63_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(NULL, acp63_sdw_pcm_resume)
|
|
};
|
|
|
|
static struct platform_driver acp63_sdw_dma_driver = {
|
|
.probe = acp63_sdw_platform_probe,
|
|
.remove = acp63_sdw_platform_remove,
|
|
.driver = {
|
|
.name = "amd_ps_sdw_dma",
|
|
.pm = &acp63_pm_ops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(acp63_sdw_dma_driver);
|
|
|
|
MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
|
|
MODULE_DESCRIPTION("AMD ACP6.3 PS SDW DMA Driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|