92 lines
3.7 KiB
ReStructuredText
92 lines
3.7 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0
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Cross-Thread Return Address Predictions
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=======================================
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Certain AMD and Hygon processors are subject to a cross-thread return address
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predictions vulnerability. When running in SMT mode and one sibling thread
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transitions out of C0 state, the other sibling thread could use return target
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predictions from the sibling thread that transitioned out of C0.
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The Spectre v2 mitigations protect the Linux kernel, as it fills the return
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address prediction entries with safe targets when context switching to the idle
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thread. However, KVM does allow a VMM to prevent exiting guest mode when
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transitioning out of C0. This could result in a guest-controlled return target
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being consumed by the sibling thread.
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Affected processors
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-------------------
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The following CPUs are vulnerable:
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- AMD Family 17h processors
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- Hygon Family 18h processors
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Related CVEs
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------------
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The following CVE entry is related to this issue:
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============== =======================================
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CVE-2022-27672 Cross-Thread Return Address Predictions
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============== =======================================
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Problem
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-------
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Affected SMT-capable processors support 1T and 2T modes of execution when SMT
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is enabled. In 2T mode, both threads in a core are executing code. For the
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processor core to enter 1T mode, it is required that one of the threads
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requests to transition out of the C0 state. This can be communicated with the
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HLT instruction or with an MWAIT instruction that requests non-C0.
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When the thread re-enters the C0 state, the processor transitions back
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to 2T mode, assuming the other thread is also still in C0 state.
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In affected processors, the return address predictor (RAP) is partitioned
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depending on the SMT mode. For instance, in 2T mode each thread uses a private
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16-entry RAP, but in 1T mode, the active thread uses a 32-entry RAP. Upon
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transition between 1T/2T mode, the RAP contents are not modified but the RAP
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pointers (which control the next return target to use for predictions) may
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change. This behavior may result in return targets from one SMT thread being
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used by RET predictions in the sibling thread following a 1T/2T switch. In
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particular, a RET instruction executed immediately after a transition to 1T may
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use a return target from the thread that just became idle. In theory, this
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could lead to information disclosure if the return targets used do not come
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from trustworthy code.
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Attack scenarios
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----------------
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An attack can be mounted on affected processors by performing a series of CALL
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instructions with targeted return locations and then transitioning out of C0
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state.
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Mitigation mechanism
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--------------------
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Before entering idle state, the kernel context switches to the idle thread. The
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context switch fills the RAP entries (referred to as the RSB in Linux) with safe
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targets by performing a sequence of CALL instructions.
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Prevent a guest VM from directly putting the processor into an idle state by
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intercepting HLT and MWAIT instructions.
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Both mitigations are required to fully address this issue.
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Mitigation control on the kernel command line
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---------------------------------------------
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Use existing Spectre v2 mitigations that will fill the RSB on context switch.
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Mitigation control for KVM - module parameter
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---------------------------------------------
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By default, the KVM hypervisor mitigates this issue by intercepting guest
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attempts to transition out of C0. A VMM can use the KVM_CAP_X86_DISABLE_EXITS
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capability to override those interceptions, but since this is not common, the
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mitigation that covers this path is not enabled by default.
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The mitigation for the KVM_CAP_X86_DISABLE_EXITS capability can be turned on
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using the boolean module parameter mitigate_smt_rsb, e.g. ``kvm.mitigate_smt_rsb=1``.
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