78 lines
1.6 KiB
YAML
78 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Xilinx clocking wizard
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maintainers:
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- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
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description:
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The clocking wizard is a soft ip clocking block of Xilinx versal. It
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reads required input clock frequencies from the devicetree and acts as clock
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clock output.
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properties:
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compatible:
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enum:
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- xlnx,clocking-wizard
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- xlnx,clocking-wizard-v5.2
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- xlnx,clocking-wizard-v6.0
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reg:
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maxItems: 1
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"#clock-cells":
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const: 1
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clocks:
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items:
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- description: clock input
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- description: axi clock
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clock-names:
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items:
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- const: clk_in1
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- const: s_axi_aclk
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xlnx,speed-grade:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [1, 2, 3]
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description:
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Speed grade of the device. Higher the speed grade faster is the FPGA device.
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xlnx,nr-outputs:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 8
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description:
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Number of outputs.
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required:
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- compatible
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- reg
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- "#clock-cells"
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- clocks
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- clock-names
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- xlnx,speed-grade
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- xlnx,nr-outputs
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additionalProperties: false
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examples:
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- |
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clock-controller@b0000000 {
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compatible = "xlnx,clocking-wizard";
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reg = <0xb0000000 0x10000>;
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#clock-cells = <1>;
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xlnx,speed-grade = <1>;
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xlnx,nr-outputs = <6>;
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clock-names = "clk_in1", "s_axi_aclk";
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clocks = <&clkc 15>, <&clkc 15>;
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};
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...
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