145 lines
3.4 KiB
YAML
145 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8qm/qxp Pixel Combiner
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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description: |
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The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
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single display controller and manipulates the two streams to support a number
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of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
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either one screen, two screens, or virtual screens. The pixel combiner is
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also responsible for generating some of the control signals for the pixel link
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output channel.
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properties:
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compatible:
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enum:
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- fsl,imx8qm-pixel-combiner
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- fsl,imx8qxp-pixel-combiner
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: apb
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power-domains:
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maxItems: 1
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patternProperties:
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"^channel@[0-1]$":
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type: object
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description: Represents a display stream of pixel combiner.
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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reg:
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description: The display stream index.
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enum: [ 0, 1 ]
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Input endpoint of the display stream.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Output endpoint of the display stream.
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required:
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- "#address-cells"
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- "#size-cells"
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- reg
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- port@0
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- port@1
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additionalProperties: false
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required:
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- compatible
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- "#address-cells"
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- "#size-cells"
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- reg
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- clocks
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- clock-names
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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pixel-combiner@56020000 {
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compatible = "fsl,imx8qxp-pixel-combiner";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x56020000 0x10000>;
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clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
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clock-names = "apb";
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power-domains = <&pd IMX_SC_R_DC_0>;
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channel@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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port@0 {
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reg = <0>;
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dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
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remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;
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};
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};
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port@1 {
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reg = <1>;
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dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
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remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;
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};
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};
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};
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channel@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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port@0 {
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reg = <0>;
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dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
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remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;
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};
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};
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port@1 {
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reg = <1>;
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dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
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remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;
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};
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};
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};
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};
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