137 lines
3.1 KiB
YAML
137 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek HDMI Encoder
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maintainers:
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- CK Hu <ck.hu@mediatek.com>
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- Jitao shi <jitao.shi@mediatek.com>
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description: |
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The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
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its parallel input.
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properties:
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compatible:
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enum:
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- mediatek,mt2701-hdmi
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- mediatek,mt7623-hdmi
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- mediatek,mt8167-hdmi
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- mediatek,mt8173-hdmi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Pixel Clock
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- description: HDMI PLL
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- description: Bit Clock
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- description: S/PDIF Clock
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clock-names:
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items:
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- const: pixel
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- const: pll
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- const: bclk
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- const: spdif
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: hdmi
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mediatek,syscon-hdmi:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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items:
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- items:
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- description: phandle to system configuration registers
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- description: register offset in the system configuration registers
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description: |
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phandle link and register offset to the system configuration registers.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: |
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Input port node. This port should be connected to a DPI output port.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: |
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Output port node. This port should be connected to the input port of a connector
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node that contains a ddc-i2c-bus property, or to the input port of an attached
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bridge chip, such as a SlimPort transmitter.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- phys
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- phy-names
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- mediatek,syscon-hdmi
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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hdmi0: hdmi@14025000 {
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compatible = "mediatek,mt8173-hdmi";
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reg = <0x14025000 0x400>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
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<&mmsys CLK_MM_HDMI_PLLCK>,
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<&mmsys CLK_MM_HDMI_AUDIO>,
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<&mmsys CLK_MM_HDMI_SPDIF>;
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clock-names = "pixel", "pll", "bclk", "spdif";
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_pin>;
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phys = <&hdmi_phy>;
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phy-names = "hdmi";
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mediatek,syscon-hdmi = <&mmsys 0x900>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi0_in: endpoint {
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remote-endpoint = <&dpi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi0_out: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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};
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};
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...
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