142 lines
4.4 KiB
Plaintext
142 lines
4.4 KiB
Plaintext
Xilinx XADC device driver
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This binding document describes the bindings for the Xilinx 7 Series XADC as well
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as the UltraScale/UltraScale+ System Monitor.
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The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
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The XADC has a DRP interface for communication. Currently two different
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frontends for the DRP interface exist. One that is only available on the ZYNQ
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family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
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on all series 7 platforms and is a softmacro with a AXI interface. This binding
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document describes the bindings for both of them since the bindings are very
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similar.
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The Xilinx System Monitor is an ADC that is found in the UltraScale and
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UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
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communication. Xilinx provides a standard IP core that can be used to access the
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System Monitor through an AXI interface in the FPGA fabric. This IP core is
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called the Xilinx System Management Wizard. This document describes the bindings
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for this IP.
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Required properties:
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- compatible: Should be one of
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* "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
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configuration interface to interface to the XADC hardmacro.
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* "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
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interface to the XADC hardmacro.
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* "xlnx,system-management-wiz-1.3": When using the
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Xilinx System Management Wizard fabric IP core to access the
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UltraScale and UltraScale+ System Monitor.
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- reg: Address and length of the register set for the device
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- interrupts: Interrupt for the XADC control interface.
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- clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
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when using the axi-xadc or the axi-system-management-wizard this must be
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the clock that provides the clock to the AXI bus interface of the core.
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Optional properties:
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- xlnx,external-mux:
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* "none": No external multiplexer is used, this is the default
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if the property is omitted.
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* "single": External multiplexer mode is used with one
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multiplexer.
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* "dual": External multiplexer mode is used with two
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multiplexers for simultaneous sampling.
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- xlnx,external-mux-channel: Configures which pair of pins is used to
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sample data in external mux mode.
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Valid values for single external multiplexer mode are:
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0: VP/VN
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1: VAUXP[0]/VAUXN[0]
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2: VAUXP[1]/VAUXN[1]
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...
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16: VAUXP[15]/VAUXN[15]
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Valid values for dual external multiplexer mode are:
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1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
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2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
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...
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8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
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This property needs to be present if the device is configured for
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external multiplexer mode (either single or dual). If the device is
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not using external multiplexer mode the property is ignored.
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- xnlx,channels: List of external channels that are connected to the ADC
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Required properties:
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* #address-cells: Should be 1.
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* #size-cells: Should be 0.
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The child nodes of this node represent the external channels which are
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connected to the ADC. If the property is no present no external
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channels will be assumed to be connected.
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Each child node represents one channel and has the following
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properties:
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Required properties:
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* reg: Pair of pins the channel is connected to.
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0: VP/VN
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1: VAUXP[0]/VAUXN[0]
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2: VAUXP[1]/VAUXN[1]
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...
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16: VAUXP[15]/VAUXN[15]
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Note each channel number should only be used at most
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once.
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Optional properties:
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* xlnx,bipolar: If set the channel is used in bipolar
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mode.
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Examples:
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xadc@f8007100 {
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compatible = "xlnx,zynq-xadc-1.00.a";
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reg = <0xf8007100 0x20>;
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interrupts = <0 7 4>;
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interrupt-parent = <&gic>;
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clocks = <&pcap_clk>;
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xlnx,channels {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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};
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channel@1 {
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reg = <1>;
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};
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channel@8 {
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reg = <8>;
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};
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};
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};
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xadc@43200000 {
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compatible = "xlnx,axi-xadc-1.00.a";
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reg = <0x43200000 0x1000>;
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interrupts = <0 53 4>;
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interrupt-parent = <&gic>;
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clocks = <&fpga1_clk>;
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xlnx,channels {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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xlnx,bipolar;
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};
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};
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};
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adc@80000000 {
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compatible = "xlnx,system-management-wiz-1.3";
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reg = <0x80000000 0x1000>;
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interrupts = <0 81 4>;
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interrupt-parent = <&gic>;
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clocks = <&fpga1_clk>;
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xlnx,channels {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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xlnx,bipolar;
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};
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};
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};
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