163 lines
3.9 KiB
YAML
163 lines
3.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
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maintainers:
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- Thierry Reding <treding@nvidia.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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const: nvidia,tegra234-mgbe
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: hypervisor
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- const: mac
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- const: xpcs
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interrupts:
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minItems: 1
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maxItems: 3
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interrupt-names:
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minItems: 1
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items:
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- const: common
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- const: macsec-ns
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- const: macsec
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clocks:
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maxItems: 12
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clock-names:
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items:
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- const: mgbe
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- const: mac
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- const: mac-divider
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- const: ptp-ref
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- const: rx-input-m
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- const: rx-input
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- const: tx
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- const: eee-pcs
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- const: rx-pcs-input
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- const: rx-pcs-m
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- const: rx-pcs
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- const: tx-pcs
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: mac
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- const: pcs
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interconnects:
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items:
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- description: memory read client
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- description: memory write client
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interconnect-names:
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items:
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- const: dma-mem
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- const: write
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iommus:
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maxItems: 1
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power-domains:
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maxItems: 1
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phy-handle: true
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phy-mode:
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contains:
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enum:
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- usxgmii
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- 10gbase-kr
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mdio:
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$ref: mdio.yaml#
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unevaluatedProperties: false
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description:
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Optional node for embedded MDIO controller.
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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- phy-handle
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- phy-mode
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra234-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/tegra234-mc.h>
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#include <dt-bindings/power/tegra234-powergate.h>
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#include <dt-bindings/reset/tegra234-reset.h>
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ethernet@6800000 {
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compatible = "nvidia,tegra234-mgbe";
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reg = <0x06800000 0x10000>,
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<0x06810000 0x10000>,
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<0x068a0000 0x10000>;
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reg-names = "hypervisor", "mac", "xpcs";
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interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "common";
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clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
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<&bpmp TEGRA234_CLK_MGBE0_MAC>,
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<&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
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<&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
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<&bpmp TEGRA234_CLK_MGBE0_TX>,
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<&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
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<&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
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clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
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"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
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"rx-pcs", "tx-pcs";
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resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
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<&bpmp TEGRA234_RESET_MGBE0_PCS>;
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reset-names = "mac", "pcs";
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
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phy-handle = <&mgbe0_phy>;
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phy-mode = "usxgmii";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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mgbe0_phy: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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#phy-cells = <0>;
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};
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};
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};
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