476 lines
14 KiB
YAML
476 lines
14 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/opp/opp-v2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Generic OPP (Operating Performance Points)
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maintainers:
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- Viresh Kumar <viresh.kumar@linaro.org>
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allOf:
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- $ref: opp-v2-base.yaml#
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properties:
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compatible:
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const: operating-points-v2
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unevaluatedProperties: false
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examples:
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- |
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/*
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* Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
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* together.
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*/
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 0>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply0>;
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operating-points-v2 = <&cpu0_opp_table0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 0>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply0>;
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operating-points-v2 = <&cpu0_opp_table0>;
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};
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};
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cpu0_opp_table0: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <975000 970000 985000>;
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opp-microamp = <70000>;
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clock-latency-ns = <300000>;
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opp-suspend;
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};
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opp-1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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opp-microvolt = <1000000 980000 1010000>;
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opp-microamp = <80000>;
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clock-latency-ns = <310000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1025000>;
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clock-latency-ns = <290000>;
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turbo-mode;
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};
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};
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- |
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/*
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* Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states
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* independently.
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*/
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,krait";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 0>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply0>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@1 {
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compatible = "qcom,krait";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 1>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply1>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@2 {
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compatible = "qcom,krait";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 2>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply2>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@3 {
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compatible = "qcom,krait";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 3>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply3>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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};
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cpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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/*
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* Missing opp-shared property means CPUs switch DVFS states
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* independently.
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*/
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <975000 970000 985000>;
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opp-microamp = <70000>;
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clock-latency-ns = <300000>;
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opp-suspend;
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};
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opp-1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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opp-microvolt = <1000000 980000 1010000>;
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opp-microamp = <80000>;
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clock-latency-ns = <310000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1025000>;
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opp-microamp = <90000>;
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clock-latency-ns = <290000>;
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turbo-mode;
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};
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};
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- |
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/*
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* Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch
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* DVFS state together.
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*/
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 0>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply0>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 0>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply0>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu@100 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <100>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 1>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply1>;
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operating-points-v2 = <&cluster1_opp>;
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};
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cpu@101 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <101>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 1>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply1>;
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operating-points-v2 = <&cluster1_opp>;
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};
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};
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cluster0_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <975000 970000 985000>;
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opp-microamp = <70000>;
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clock-latency-ns = <300000>;
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opp-suspend;
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};
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opp-1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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opp-microvolt = <1000000 980000 1010000>;
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opp-microamp = <80000>;
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clock-latency-ns = <310000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1025000>;
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opp-microamp = <90000>;
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clock-latency-ns = <290000>;
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turbo-mode;
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};
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};
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cluster1_opp: opp-table-1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1050000 1045000 1055000>;
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opp-microamp = <95000>;
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clock-latency-ns = <400000>;
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opp-suspend;
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};
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opp-1400000000 {
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opp-hz = /bits/ 64 <1400000000>;
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opp-microvolt = <1075000>;
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opp-microamp = <100000>;
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clock-latency-ns = <400000>;
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};
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opp-1500000000 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <1100000 1010000 1110000>;
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opp-microamp = <95000>;
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clock-latency-ns = <400000>;
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turbo-mode;
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};
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};
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- |
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/* Example 4: Handling multiple regulators */
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "foo,cpu-type";
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device_type = "cpu";
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reg = <0>;
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vcc0-supply = <&cpu_supply0>;
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vcc1-supply = <&cpu_supply1>;
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vcc2-supply = <&cpu_supply2>;
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operating-points-v2 = <&cpu0_opp_table4>;
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};
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};
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cpu0_opp_table4: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <970000>, /* Supply 0 */
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<960000>, /* Supply 1 */
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<960000>; /* Supply 2 */
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opp-microamp = <70000>, /* Supply 0 */
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<70000>, /* Supply 1 */
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<70000>; /* Supply 2 */
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clock-latency-ns = <300000>;
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};
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/* OR */
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opp-1000000001 {
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opp-hz = /bits/ 64 <1000000001>;
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opp-microvolt = <975000 970000 985000>, /* Supply 0 */
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<965000 960000 975000>, /* Supply 1 */
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<965000 960000 975000>; /* Supply 2 */
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opp-microamp = <70000>, /* Supply 0 */
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<70000>, /* Supply 1 */
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<70000>; /* Supply 2 */
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clock-latency-ns = <300000>;
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};
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/* OR */
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opp-1000000002 {
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opp-hz = /bits/ 64 <1000000002>;
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opp-microvolt = <975000 970000 985000>, /* Supply 0 */
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<965000 960000 975000>, /* Supply 1 */
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<965000 960000 975000>; /* Supply 2 */
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opp-microamp = <70000>, /* Supply 0 */
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<0>, /* Supply 1 doesn't need this */
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<70000>; /* Supply 2 */
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clock-latency-ns = <300000>;
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};
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};
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/*
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* Example 5: opp-supported-hw
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* (example: three level hierarchy of versions: cuts, substrate and process)
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*/
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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cpu-supply = <&cpu_supply>;
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operating-points-v2 = <&cpu0_opp_table_slow>;
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};
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};
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cpu0_opp_table_slow: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-600000000 {
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/*
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* Supports all substrate and process versions for 0xF
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* cuts, i.e. only first four cuts.
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*/
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opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF>;
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opp-hz = /bits/ 64 <600000000>;
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};
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opp-800000000 {
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/*
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* Supports:
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* - cuts: only one, 6th cut (represented by 6th bit).
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* - substrate: supports 16 different substrate versions
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* - process: supports 9 different process versions
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*/
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opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0>;
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opp-hz = /bits/ 64 <800000000>;
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};
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opp-900000000 {
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/*
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* Supports:
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* - All cuts and substrate where process version is 0x2.
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* - All cuts and process where substrate version is 0x2.
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*/
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opp-supported-hw = <0xFFFFFFFF 0xFFFFFFFF 0x02>,
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<0xFFFFFFFF 0x01 0xFFFFFFFF>;
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opp-hz = /bits/ 64 <900000000>;
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};
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};
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/*
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* Example 6: opp-microvolt-<name>, opp-microamp-<name>:
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* (example: device with two possible microvolt ranges: slow and fast)
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*/
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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operating-points-v2 = <&cpu0_opp_table6>;
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};
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};
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cpu0_opp_table6: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt-slow = <915000 900000 925000>;
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opp-microvolt-fast = <975000 970000 985000>;
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opp-microamp-slow = <70000>;
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opp-microamp-fast = <71000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */
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<925000 910000 935000>; /* Supply vcc1 */
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opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */
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<965000 960000 975000>; /* Supply vcc1 */
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opp-microamp = <70000>; /* Will be used for both slow/fast */
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};
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};
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- |
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/*
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* Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware,
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* distinct clock controls but two sets of clock/voltage/current lines.
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*/
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x100>;
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next-level-cache = <&A53_L2>;
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clocks = <&dvfs_controller 0>;
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operating-points-v2 = <&cpu_opp0_table>;
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};
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cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x101>;
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next-level-cache = <&A53_L2>;
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clocks = <&dvfs_controller 1>;
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operating-points-v2 = <&cpu_opp0_table>;
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};
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cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x102>;
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next-level-cache = <&A53_L2>;
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clocks = <&dvfs_controller 2>;
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operating-points-v2 = <&cpu_opp1_table>;
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};
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cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x103>;
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next-level-cache = <&A53_L2>;
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clocks = <&dvfs_controller 3>;
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operating-points-v2 = <&cpu_opp1_table>;
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};
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};
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cpu_opp0_table: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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};
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cpu_opp1_table: opp-table-1 {
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compatible = "operating-points-v2";
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opp-shared;
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};
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...
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