164 lines
5.1 KiB
YAML
164 lines
5.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SM8550 TLMM block
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maintainers:
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- Abel Vesa <abel.vesa@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,sm8550-tlmm
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reg:
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maxItems: 1
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interrupts: true
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 105
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gpio-line-names:
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maxItems: 210
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sm8550-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sm8550-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sm8550-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
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- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ aon_cci, aoss_cti, atest_char, atest_usb,
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audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk,
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cam_aon_mclk4, cam_mclk, cci_async_in, cci_i2c_scl,
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cci_i2c_sda, cci_timer, cmu_rng, coex_uart1_rx,
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coex_uart1_tx, coex_uart2_rx, coex_uart2_tx,
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cri_trng, dbg_out_clk, ddr_bist_complete,
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ddr_bist_fail, ddr_bist_start, ddr_bist_stop,
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ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot,
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gcc_gp1, gcc_gp2, gcc_gp3, gpio, i2chub0_se0,
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i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4,
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i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
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i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck,
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i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws,
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ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0_out,
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mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
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mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
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pcie0_clk_req_n, pcie1_clk_req_n, phase_flag,
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pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
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prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
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qlink0_enable, qlink0_request, qlink0_wmss,
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qlink1_enable, qlink1_request, qlink1_wmss,
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qlink2_enable, qlink2_request, qlink2_wmss,
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qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs,
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qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
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qup1_se5, qup1_se6, qup1_se7, qup2_se0,
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qup2_se0_l0_mira, qup2_se0_l0_mirb, qup2_se0_l1_mira,
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qup2_se0_l1_mirb, qup2_se0_l2_mira, qup2_se0_l2_mirb,
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qup2_se0_l3_mira, qup2_se0_l3_mirb, qup2_se1,
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qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
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qup2_se7, sd_write_protect, sdc40, sdc41, sdc42,
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sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4,
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tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
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tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
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tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3,
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uim0_clk, uim0_data, uim0_present, uim0_reset,
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uim1_clk, uim1_data, uim1_present, uim1_reset,
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usb1_hs, usb_phy, vfr_0, vfr_1, vsense_trigger_mirnat ]
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength: true
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input-enable: true
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output-high: true
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output-low: true
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required:
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- pins
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,sm8550-tlmm";
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reg = <0x0f100000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 211>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-wo-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-state {
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rx-pins {
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pins = "gpio26";
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function = "qup2_se7";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio27";
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function = "qup2_se7";
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bias-disable;
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};
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};
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};
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...
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