164 lines
4.1 KiB
YAML
164 lines
4.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: GENI Serial Engine QUP Wrapper Controller
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
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is a programmable module for supporting a wide range of serial interfaces
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like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
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Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
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Wrapper controller is modeled as a node with zero or more child nodes each
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representing a serial engine.
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properties:
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compatible:
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enum:
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- qcom,geni-se-qup
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- qcom,geni-se-i2c-master-hub
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reg:
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description: QUP wrapper common register address and length.
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maxItems: 1
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clock-names:
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minItems: 1
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maxItems: 2
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clocks:
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minItems: 1
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maxItems: 2
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"#address-cells":
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const: 2
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"#size-cells":
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const: 2
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ranges: true
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interconnects:
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maxItems: 1
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interconnect-names:
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const: qup-core
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iommus:
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maxItems: 1
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required:
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- compatible
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- reg
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- clock-names
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- clocks
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- "#address-cells"
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- "#size-cells"
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- ranges
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patternProperties:
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"spi@[0-9a-f]+$":
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type: object
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description: GENI serial engine based SPI controller. SPI in master mode
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supports up to 50MHz, up to four chip selects, programmable
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data path from 4 bits to 32 bits and numerous protocol
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variants.
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$ref: /schemas/spi/qcom,spi-geni-qcom.yaml#
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"i2c@[0-9a-f]+$":
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type: object
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description: GENI serial engine based I2C controller.
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$ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#
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"serial@[0-9a-f]+$":
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type: object
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description: GENI Serial Engine based UART Controller.
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$ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: qcom,geni-se-i2c-master-hub
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then:
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properties:
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clock-names:
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items:
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- const: s-ahb
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clocks:
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items:
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- description: Slave AHB Clock
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iommus: false
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patternProperties:
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"spi@[0-9a-f]+$": false
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"serial@[0-9a-f]+$": false
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else:
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properties:
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clock-names:
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items:
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- const: m-ahb
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- const: s-ahb
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clocks:
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items:
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- description: Master AHB Clock
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- description: Slave AHB Clock
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0 0x008c0000 0 0x6000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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i2c0: i2c@a94000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0xa94000 0 0x4000>;
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_i2c_5_active>;
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pinctrl-1 = <&qup_1_i2c_5_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: serial@a88000 {
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compatible = "qcom,geni-uart";
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reg = <0 0xa88000 0 0x7000>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_uart_3_active>;
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pinctrl-1 = <&qup_1_uart_3_sleep>;
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};
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};
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};
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...
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