120 lines
2.9 KiB
YAML
120 lines
2.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
|
|
%YAML 1.2
|
|
---
|
|
$id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
|
|
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|
|
|
title: TI wrapper module for the Cadence USBSS-DRD controller
|
|
|
|
maintainers:
|
|
- Roger Quadros <rogerq@kernel.org>
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- const: ti,j721e-usb
|
|
- const: ti,am64-usb
|
|
- items:
|
|
- const: ti,j721e-usb
|
|
- const: ti,am64-usb
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
ranges: true
|
|
|
|
power-domains:
|
|
description:
|
|
PM domain provider node and an args specifier containing
|
|
the USB device id value. See,
|
|
Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
description: Clock phandles to usb2_refclk and lpm_clk
|
|
minItems: 2
|
|
maxItems: 2
|
|
|
|
clock-names:
|
|
items:
|
|
- const: ref
|
|
- const: lpm
|
|
|
|
ti,usb2-only:
|
|
description:
|
|
If present, it restricts the controller to USB2.0 mode of
|
|
operation. Must be present if USB3 PHY is not available
|
|
for USB.
|
|
type: boolean
|
|
|
|
ti,vbus-divider:
|
|
description:
|
|
Should be present if USB VBUS line is connected to the
|
|
VBUS pin of the SoC via a 1/3 voltage divider.
|
|
type: boolean
|
|
|
|
assigned-clocks:
|
|
maxItems: 1
|
|
|
|
assigned-clock-parents:
|
|
maxItems: 1
|
|
|
|
'#address-cells':
|
|
const: 2
|
|
|
|
'#size-cells':
|
|
const: 2
|
|
|
|
dma-coherent: true
|
|
|
|
patternProperties:
|
|
"^usb@":
|
|
type: object
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- power-domains
|
|
- clocks
|
|
- clock-names
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
bus {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
cdns_usb@4104000 {
|
|
compatible = "ti,j721e-usb";
|
|
reg = <0x00 0x4104000 0x00 0x100>;
|
|
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
|
|
clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
|
|
clock-names = "ref", "lpm";
|
|
assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
|
|
assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
usb@6000000 {
|
|
compatible = "cdns,usb3";
|
|
reg = <0x00 0x6000000 0x00 0x10000>,
|
|
<0x00 0x6010000 0x00 0x10000>,
|
|
<0x00 0x6020000 0x00 0x10000>;
|
|
reg-names = "otg", "xhci", "dev";
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
|
|
interrupt-names = "host",
|
|
"peripheral",
|
|
"otg";
|
|
maximum-speed = "super-speed";
|
|
dr_mode = "otg";
|
|
};
|
|
};
|
|
};
|