492 lines
13 KiB
Plaintext
492 lines
13 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7629-clk.h>
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#include <dt-bindings/power/mt7622-power.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt7629-resets.h>
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/ {
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compatible = "mediatek,mt7629";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt6589-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clock-frequency = <1250000000>;
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cci-control-port = <&cci_control2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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clock-frequency = <1250000000>;
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cci-control-port = <&cci_control2>;
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};
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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clk20m: oscillator-0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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clock-output-names = "clk20m";
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};
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clk40m: oscillator-1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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clock-output-names = "clkxtal";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <20000000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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infracfg: syscon@10000000 {
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compatible = "mediatek,mt7629-infracfg", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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pericfg: syscon@10002000 {
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compatible = "mediatek,mt7629-pericfg", "syscon";
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reg = <0x10002000 0x1000>;
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#clock-cells = <1>;
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};
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scpsys: power-controller@10006000 {
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compatible = "mediatek,mt7629-scpsys",
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"mediatek,mt7622-scpsys";
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#power-domain-cells = <1>;
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reg = <0x10006000 0x1000>;
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clocks = <&topckgen CLK_TOP_HIF_SEL>;
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clock-names = "hif_sel";
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assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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infracfg = <&infracfg>;
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};
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timer: timer@10009000 {
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compatible = "mediatek,mt7629-timer",
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"mediatek,mt6765-timer";
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reg = <0x10009000 0x60>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk20m>;
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clock-names = "clk20m";
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};
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sysirq: interrupt-controller@10200a80 {
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compatible = "mediatek,mt7629-sysirq",
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"mediatek,mt6577-sysirq";
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reg = <0x10200a80 0x20>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt7629-apmixedsys", "syscon";
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reg = <0x10209000 0x1000>;
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#clock-cells = <1>;
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};
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rng: rng@1020f000 {
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compatible = "mediatek,mt7629-rng",
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"mediatek,mt7623-rng";
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reg = <0x1020f000 0x100>;
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clocks = <&infracfg CLK_INFRA_TRNG_PD>;
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clock-names = "rng";
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};
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topckgen: syscon@10210000 {
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compatible = "mediatek,mt7629-topckgen", "syscon";
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reg = <0x10210000 0x1000>;
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#clock-cells = <1>;
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};
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watchdog: watchdog@10212000 {
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compatible = "mediatek,mt7629-wdt",
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"mediatek,mt6589-wdt";
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reg = <0x10212000 0x100>;
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};
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pio: pinctrl@10217000 {
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compatible = "mediatek,mt7629-pinctrl";
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reg = <0x10217000 0x8000>,
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<0x10005000 0x1000>;
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reg-names = "base", "eint";
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gpio-controller;
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gpio-ranges = <&pio 0 0 79>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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gic: interrupt-controller@10300000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10310000 0x1000>,
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<0x10320000 0x1000>,
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<0x10340000 0x2000>,
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<0x10360000 0x2000>;
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};
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cci: cci@10390000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10390000 0x1000>;
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ranges = <0 0x10390000 0x10000>;
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cci_control0: slave-if@1000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace-lite";
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reg = <0x1000 0x1000>;
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};
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cci_control1: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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};
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cci_control2: slave-if@5000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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pmu@9000 {
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compatible = "arm,cci-400-pmu,r1";
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reg = <0x9000 0x5000>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7629-uart",
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"mediatek,mt6577-uart";
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reg = <0x11002000 0x400>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART0_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt7629-uart",
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"mediatek,mt6577-uart";
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reg = <0x11003000 0x400>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART1_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt7629-uart",
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"mediatek,mt6577-uart";
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reg = <0x11004000 0x400>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART2_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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pwm: pwm@11006000 {
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compatible = "mediatek,mt7629-pwm";
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reg = <0x11006000 0x1000>;
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#pwm-cells = <2>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>,
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<&pericfg CLK_PERI_PWM_PD>,
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<&pericfg CLK_PERI_PWM1_PD>;
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clock-names = "top", "main", "pwm1";
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assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
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assigned-clock-parents =
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<&topckgen CLK_TOP_UNIVPLL2_D4>;
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status = "disabled";
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};
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i2c: i2c@11007000 {
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compatible = "mediatek,mt7629-i2c",
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"mediatek,mt2712-i2c";
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reg = <0x11007000 0x90>,
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<0x11000100 0x80>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <4>;
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clocks = <&pericfg CLK_PERI_I2C0_PD>,
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<&pericfg CLK_PERI_AP_DMA_PD>;
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clock-names = "main", "dma";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi: spi@1100a000 {
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compatible = "mediatek,mt7629-spi",
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"mediatek,mt7622-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1100a000 0x100>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI0_SEL>,
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<&pericfg CLK_PERI_SPI0_PD>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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qspi: spi@11014000 {
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compatible = "mediatek,mt7629-nor",
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"mediatek,mt8173-nor";
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reg = <0x11014000 0xe0>;
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clocks = <&pericfg CLK_PERI_FLASH_PD>,
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<&topckgen CLK_TOP_FLASH_SEL>;
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clock-names = "spi", "sf";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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ssusbsys: syscon@1a000000 {
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compatible = "mediatek,mt7629-ssusbsys", "syscon";
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reg = <0x1a000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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ssusb: usb@1a0c0000 {
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compatible = "mediatek,mt7629-xhci",
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"mediatek,mtk-xhci";
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reg = <0x1a0c0000 0x01000>,
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<0x1a0c3e00 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
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<&ssusbsys CLK_SSUSB_REF_EN>,
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<&ssusbsys CLK_SSUSB_MCU_EN>,
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<&ssusbsys CLK_SSUSB_DMA_EN>;
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clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
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<&topckgen CLK_TOP_SATA_SEL>,
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<&topckgen CLK_TOP_HIF_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
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<&topckgen CLK_TOP_UNIVPLL2_D4>,
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<&topckgen CLK_TOP_UNIVPLL1_D2>;
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
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phys = <&u2port0 PHY_TYPE_USB2>,
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<&u3port0 PHY_TYPE_USB3>;
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status = "disabled";
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};
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u3phy0: t-phy@1a0c4000 {
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compatible = "mediatek,mt7629-tphy",
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"mediatek,generic-tphy-v2";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1a0c4000 0xe00>;
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status = "disabled";
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u2port0: usb-phy@0 {
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reg = <0 0x700>;
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clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u3port0: usb-phy@700 {
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reg = <0x700 0x700>;
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clocks = <&clk20m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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};
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pciesys: syscon@1a100800 {
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compatible = "mediatek,mt7629-pciesys", "syscon";
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reg = <0x1a100800 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pciecfg: pciecfg@1a140000 {
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compatible = "mediatek,generic-pciecfg", "syscon";
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reg = <0x1a140000 0x1000>;
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};
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pcie1: pcie@1a145000 {
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compatible = "mediatek,mt7629-pcie";
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device_type = "pci";
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reg = <0x1a145000 0x1000>;
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reg-names = "port1";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "pcie_irq";
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clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
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<&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P1_AUX_EN>,
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<&pciesys CLK_PCIE_P1_AXI_EN>,
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<&pciesys CLK_PCIE_P1_OBFF_EN>,
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<&pciesys CLK_PCIE_P1_PIPE_EN>;
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clock-names = "sys_ck1", "ahb_ck1",
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"aux_ck1", "axi_ck1",
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"obff_ck1", "pipe_ck1";
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assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
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<&topckgen CLK_TOP_AXI_SEL>,
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<&topckgen CLK_TOP_HIF_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
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<&topckgen CLK_TOP_SYSPLL1_D2>,
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<&topckgen CLK_TOP_UNIVPLL1_D2>;
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phys = <&pcieport1 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy1";
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pciephy1: t-phy@1a14a000 {
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compatible = "mediatek,mt7629-tphy",
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"mediatek,generic-tphy-v2";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1a14a000 0x1000>;
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status = "disabled";
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pcieport1: pcie-phy@0 {
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reg = <0 0x1000>;
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clocks = <&clk20m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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};
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt7629-ethsys", "syscon";
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reg = <0x1b000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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eth: ethernet@1b100000 {
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compatible = "mediatek,mt7629-eth","syscon";
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reg = <0x1b100000 0x20000>;
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_ETH_SEL>,
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<&topckgen CLK_TOP_F10M_REF_SEL>,
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<ðsys CLK_ETH_ESW_EN>,
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<ðsys CLK_ETH_GP0_EN>,
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<ðsys CLK_ETH_GP1_EN>,
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<ðsys CLK_ETH_GP2_EN>,
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<ðsys CLK_ETH_FE_EN>,
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<&sgmiisys0 CLK_SGMII_TX_EN>,
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<&sgmiisys0 CLK_SGMII_RX_EN>,
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<&sgmiisys0 CLK_SGMII_CDR_REF>,
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<&sgmiisys0 CLK_SGMII_CDR_FB>,
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<&sgmiisys1 CLK_SGMII_TX_EN>,
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<&sgmiisys1 CLK_SGMII_RX_EN>,
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<&sgmiisys1 CLK_SGMII_CDR_REF>,
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<&sgmiisys1 CLK_SGMII_CDR_FB>,
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<&apmixedsys CLK_APMIXED_SGMIPLL>,
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|
<&apmixedsys CLK_APMIXED_ETH2PLL>;
|
|
clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1",
|
|
"gp2", "fe", "sgmii_tx250m", "sgmii_rx250m",
|
|
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
|
"sgmii2_tx250m", "sgmii2_rx250m",
|
|
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
|
"sgmii_ck", "eth2pll";
|
|
assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
|
|
<&topckgen CLK_TOP_F10M_REF_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
|
|
<&topckgen CLK_TOP_SGMIIPLL_D2>;
|
|
power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
|
|
mediatek,ethsys = <ðsys>;
|
|
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
|
mediatek,infracfg = <&infracfg>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sgmiisys0: syscon@1b128000 {
|
|
compatible = "mediatek,mt7629-sgmiisys", "syscon";
|
|
reg = <0x1b128000 0x3000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sgmiisys1: syscon@1b130000 {
|
|
compatible = "mediatek,mt7629-sgmiisys", "syscon";
|
|
reg = <0x1b130000 0x3000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
};
|