595 lines
15 KiB
C
595 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/arm/kernel/bios32.c
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*
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* PCI bios-type initialisation for PCI machines
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*
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* Bits taken from various places.
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*/
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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#include <asm/mach/pci.h>
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static int debug_pci;
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/*
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* We can't use pci_get_device() here since we are
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* called from interrupt context.
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*/
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static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 status;
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/*
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* ignore host bridge - we handle
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* that separately
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*/
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if (dev->bus->number == 0 && dev->devfn == 0)
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continue;
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pci_read_config_word(dev, PCI_STATUS, &status);
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if (status == 0xffff)
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continue;
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if ((status & status_mask) == 0)
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continue;
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/* clear the status errors */
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pci_write_config_word(dev, PCI_STATUS, status & status_mask);
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if (warn)
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printk("(%s: %04X) ", pci_name(dev), status);
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}
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list_for_each_entry(dev, &bus->devices, bus_list)
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if (dev->subordinate)
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pcibios_bus_report_status(dev->subordinate, status_mask, warn);
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}
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void pcibios_report_status(u_int status_mask, int warn)
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{
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struct pci_bus *bus;
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list_for_each_entry(bus, &pci_root_buses, node)
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pcibios_bus_report_status(bus, status_mask, warn);
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}
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/*
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* We don't use this to fix the device, but initialisation of it.
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* It's not the correct use for this, but it works.
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* Note that the arbiter/ISA bridge appears to be buggy, specifically in
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* the following area:
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* 1. park on CPU
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* 2. ISA bridge ping-pong
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* 3. ISA bridge master handling of target RETRY
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*
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* Bug 3 is responsible for the sound DMA grinding to a halt. We now
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* live with bug 2.
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*/
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static void pci_fixup_83c553(struct pci_dev *dev)
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{
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/*
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* Set memory region to start at address 0, and enable IO
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*/
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
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pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
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dev->resource[0].end -= dev->resource[0].start;
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dev->resource[0].start = 0;
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/*
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* All memory requests from ISA to be channelled to PCI
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*/
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pci_write_config_byte(dev, 0x48, 0xff);
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/*
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* Enable ping-pong on bus master to ISA bridge transactions.
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* This improves the sound DMA substantially. The fixed
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* priority arbiter also helps (see below).
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*/
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pci_write_config_byte(dev, 0x42, 0x01);
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/*
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* Enable PCI retry
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*/
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pci_write_config_byte(dev, 0x40, 0x22);
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/*
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* We used to set the arbiter to "park on last master" (bit
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* 1 set), but unfortunately the CyberPro does not park the
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* bus. We must therefore park on CPU. Unfortunately, this
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* may trigger yet another bug in the 553.
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*/
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pci_write_config_byte(dev, 0x83, 0x02);
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/*
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* Make the ISA DMA request lowest priority, and disable
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* rotating priorities completely.
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*/
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pci_write_config_byte(dev, 0x80, 0x11);
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pci_write_config_byte(dev, 0x81, 0x00);
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/*
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* Route INTA input to IRQ 11, and set IRQ11 to be level
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* sensitive.
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*/
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pci_write_config_word(dev, 0x44, 0xb000);
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outb(0x08, 0x4d1);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
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static void pci_fixup_unassign(struct pci_dev *dev)
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{
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dev->resource[0].end -= dev->resource[0].start;
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dev->resource[0].start = 0;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
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/*
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* Prevent the PCI layer from seeing the resources allocated to this device
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* if it is the host bridge by marking it as such. These resources are of
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* no consequence to the PCI layer (they are handled elsewhere).
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*/
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static void pci_fixup_dec21285(struct pci_dev *dev)
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{
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int i;
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if (dev->devfn == 0) {
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dev->class &= 0xff;
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dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
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/*
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* PCI IDE controllers use non-standard I/O port decoding, respect it.
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*/
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static void pci_fixup_ide_bases(struct pci_dev *dev)
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{
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struct resource *r;
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int i;
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if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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r = dev->resource + i;
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if ((r->start & ~0x80) == 0x374) {
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r->start |= 2;
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r->end = r->start;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
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/*
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* Put the DEC21142 to sleep
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*/
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static void pci_fixup_dec21142(struct pci_dev *dev)
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{
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pci_write_config_dword(dev, 0x40, 0x80000000);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
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/*
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* The CY82C693 needs some rather major fixups to ensure that it does
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* the right thing. Idea from the Alpha people, with a few additions.
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*
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* We ensure that the IDE base registers are set to 1f0/3f4 for the
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* primary bus, and 170/374 for the secondary bus. Also, hide them
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* from the PCI subsystem view as well so we won't try to perform
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* our own auto-configuration on them.
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*
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* In addition, we ensure that the PCI IDE interrupts are routed to
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* IRQ 14 and IRQ 15 respectively.
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*
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* The above gets us to a point where the IDE on this device is
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* functional. However, The CY82C693U _does not work_ in bus
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* master mode without locking the PCI bus solid.
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*/
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static void pci_fixup_cy82c693(struct pci_dev *dev)
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{
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if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
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u32 base0, base1;
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if (dev->class & 0x80) { /* primary */
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base0 = 0x1f0;
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base1 = 0x3f4;
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} else { /* secondary */
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base0 = 0x170;
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base1 = 0x374;
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}
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
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base0 | PCI_BASE_ADDRESS_SPACE_IO);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
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base1 | PCI_BASE_ADDRESS_SPACE_IO);
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dev->resource[0].start = 0;
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dev->resource[0].end = 0;
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dev->resource[0].flags = 0;
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dev->resource[1].start = 0;
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dev->resource[1].end = 0;
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dev->resource[1].flags = 0;
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} else if (PCI_FUNC(dev->devfn) == 0) {
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/*
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* Setup IDE IRQ routing.
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*/
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pci_write_config_byte(dev, 0x4b, 14);
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pci_write_config_byte(dev, 0x4c, 15);
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/*
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* Disable FREQACK handshake, enable USB.
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*/
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pci_write_config_byte(dev, 0x4d, 0x41);
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/*
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* Enable PCI retry, and PCI post-write buffer.
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*/
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pci_write_config_byte(dev, 0x44, 0x17);
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/*
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* Enable ISA master and DMA post write buffering.
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*/
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pci_write_config_byte(dev, 0x45, 0x03);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
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/*
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* If the bus contains any of these devices, then we must not turn on
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* parity checking of any kind. Currently this is CyberPro 20x0 only.
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*/
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static inline int pdev_bad_for_parity(struct pci_dev *dev)
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{
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return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
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(dev->device == PCI_DEVICE_ID_INTERG_2000 ||
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dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
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(dev->vendor == PCI_VENDOR_ID_ITE &&
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dev->device == PCI_DEVICE_ID_ITE_8152));
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}
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/*
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* pcibios_fixup_bus - Called after each bus is probed,
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* but before its children are examined.
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*/
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
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/*
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* Walk the devices on this bus, working out what we can
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* and can't support.
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*/
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 status;
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pci_read_config_word(dev, PCI_STATUS, &status);
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/*
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* If any device on this bus does not support fast back
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* to back transfers, then the bus as a whole is not able
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* to support them. Having fast back to back transfers
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* on saves us one PCI cycle per transaction.
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*/
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if (!(status & PCI_STATUS_FAST_BACK))
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features &= ~PCI_COMMAND_FAST_BACK;
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if (pdev_bad_for_parity(dev))
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features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
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switch (dev->class >> 8) {
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case PCI_CLASS_BRIDGE_PCI:
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
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status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
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status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
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break;
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case PCI_CLASS_BRIDGE_CARDBUS:
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pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
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status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
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pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
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break;
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}
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}
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/*
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* Now walk the devices again, this time setting them up.
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*/
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 cmd;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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cmd |= features;
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
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L1_CACHE_BYTES >> 2);
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}
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/*
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* Propagate the flags to the PCI bridge.
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*/
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if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
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if (features & PCI_COMMAND_FAST_BACK)
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bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
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if (features & PCI_COMMAND_PARITY)
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bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
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}
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/*
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* Report what we did for this bus
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*/
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pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
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bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
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}
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EXPORT_SYMBOL(pcibios_fixup_bus);
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/*
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* Swizzle the device pin each time we cross a bridge. If a platform does
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* not provide a swizzle function, we perform the standard PCI swizzling.
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*
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* The default swizzling walks up the bus tree one level at a time, applying
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* the standard swizzle function at each step, stopping when it finds the PCI
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* root bus. This will return the slot number of the bridge device on the
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* root bus and the interrupt pin on that device which should correspond
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* with the downstream device interrupt.
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*
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* Platforms may override this, in which case the slot and pin returned
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* depend entirely on the platform code. However, please note that the
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* PCI standard swizzle is implemented on plug-in cards and Cardbus based
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* PCI extenders, so it can not be ignored.
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*/
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static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
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{
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struct pci_sys_data *sys = dev->sysdata;
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int slot, oldpin = *pin;
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if (sys->swizzle)
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slot = sys->swizzle(dev, pin);
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else
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slot = pci_common_swizzle(dev, pin);
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if (debug_pci)
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printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
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pci_name(dev), oldpin, *pin, slot);
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return slot;
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}
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/*
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* Map a slot/pin to an IRQ.
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*/
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static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct pci_sys_data *sys = dev->sysdata;
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int irq = -1;
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if (sys->map_irq)
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irq = sys->map_irq(dev, slot, pin);
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if (debug_pci)
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printk("PCI: %s mapping slot %d pin %d => irq %d\n",
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pci_name(dev), slot, pin, irq);
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return irq;
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}
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static int pcibios_init_resource(int busnr, struct pci_sys_data *sys)
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{
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int ret;
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struct resource_entry *window;
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if (list_empty(&sys->resources)) {
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pci_add_resource_offset(&sys->resources,
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&iomem_resource, sys->mem_offset);
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}
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resource_list_for_each_entry(window, &sys->resources)
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if (resource_type(window->res) == IORESOURCE_IO)
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return 0;
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sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
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sys->io_res.end = (busnr + 1) * SZ_64K - 1;
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sys->io_res.flags = IORESOURCE_IO;
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sys->io_res.name = sys->io_res_name;
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sprintf(sys->io_res_name, "PCI%d I/O", busnr);
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ret = request_resource(&ioport_resource, &sys->io_res);
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if (ret) {
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pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
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return ret;
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}
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pci_add_resource_offset(&sys->resources, &sys->io_res,
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sys->io_offset);
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return 0;
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}
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static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
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struct list_head *head)
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{
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struct pci_sys_data *sys = NULL;
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int ret;
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int nr, busnr;
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for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
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struct pci_host_bridge *bridge;
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bridge = pci_alloc_host_bridge(sizeof(struct pci_sys_data));
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if (WARN(!bridge, "PCI: unable to allocate bridge!"))
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break;
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sys = pci_host_bridge_priv(bridge);
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sys->busnr = busnr;
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sys->swizzle = hw->swizzle;
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sys->map_irq = hw->map_irq;
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INIT_LIST_HEAD(&sys->resources);
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if (hw->private_data)
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sys->private_data = hw->private_data[nr];
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ret = hw->setup(nr, sys);
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if (ret > 0) {
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ret = pcibios_init_resource(nr, sys);
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if (ret) {
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pci_free_host_bridge(bridge);
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break;
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}
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bridge->map_irq = pcibios_map_irq;
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bridge->swizzle_irq = pcibios_swizzle;
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if (hw->scan)
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ret = hw->scan(nr, bridge);
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else {
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list_splice_init(&sys->resources,
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&bridge->windows);
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bridge->dev.parent = parent;
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bridge->sysdata = sys;
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bridge->busnr = sys->busnr;
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bridge->ops = hw->ops;
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ret = pci_scan_root_bus_bridge(bridge);
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}
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if (WARN(ret < 0, "PCI: unable to scan bus!")) {
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pci_free_host_bridge(bridge);
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break;
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}
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sys->bus = bridge->bus;
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busnr = sys->bus->busn_res.end + 1;
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list_add(&sys->node, head);
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} else {
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pci_free_host_bridge(bridge);
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if (ret < 0)
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break;
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}
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}
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}
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void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
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{
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struct pci_sys_data *sys;
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LIST_HEAD(head);
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pci_add_flags(PCI_REASSIGN_ALL_BUS);
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if (hw->preinit)
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hw->preinit();
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pcibios_init_hw(parent, hw, &head);
|
|
if (hw->postinit)
|
|
hw->postinit();
|
|
|
|
list_for_each_entry(sys, &head, node) {
|
|
struct pci_bus *bus = sys->bus;
|
|
|
|
/*
|
|
* We insert PCI resources into the iomem_resource and
|
|
* ioport_resource trees in either pci_bus_claim_resources()
|
|
* or pci_bus_assign_resources().
|
|
*/
|
|
if (pci_has_flag(PCI_PROBE_ONLY)) {
|
|
pci_bus_claim_resources(bus);
|
|
} else {
|
|
struct pci_bus *child;
|
|
|
|
pci_bus_size_bridges(bus);
|
|
pci_bus_assign_resources(bus);
|
|
|
|
list_for_each_entry(child, &bus->children, node)
|
|
pcie_bus_configure_settings(child);
|
|
}
|
|
|
|
pci_bus_add_devices(bus);
|
|
}
|
|
}
|
|
|
|
#ifndef CONFIG_PCI_HOST_ITE8152
|
|
void pcibios_set_master(struct pci_dev *dev)
|
|
{
|
|
/* No special bus mastering setup handling */
|
|
}
|
|
#endif
|
|
|
|
char * __init pcibios_setup(char *str)
|
|
{
|
|
if (!strcmp(str, "debug")) {
|
|
debug_pci = 1;
|
|
return NULL;
|
|
}
|
|
return str;
|
|
}
|
|
|
|
/*
|
|
* From arch/i386/kernel/pci-i386.c:
|
|
*
|
|
* We need to avoid collisions with `mirrored' VGA ports
|
|
* and other strange ISA hardware, so we always want the
|
|
* addresses to be allocated in the 0x000-0x0ff region
|
|
* modulo 0x400.
|
|
*
|
|
* Why? Because some silly external IO cards only decode
|
|
* the low 10 bits of the IO address. The 0x00-0xff region
|
|
* is reserved for motherboard devices that decode all 16
|
|
* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
|
|
* but we want to try to avoid allocating at 0x2900-0x2bff
|
|
* which might be mirrored at 0x0100-0x03ff..
|
|
*/
|
|
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
|
|
resource_size_t size, resource_size_t align)
|
|
{
|
|
struct pci_dev *dev = data;
|
|
resource_size_t start = res->start;
|
|
struct pci_host_bridge *host_bridge;
|
|
|
|
if (res->flags & IORESOURCE_IO && start & 0x300)
|
|
start = (start + 0x3ff) & ~0x3ff;
|
|
|
|
start = (start + align - 1) & ~(align - 1);
|
|
|
|
host_bridge = pci_find_host_bridge(dev->bus);
|
|
|
|
if (host_bridge->align_resource)
|
|
return host_bridge->align_resource(dev, res,
|
|
start, size, align);
|
|
|
|
return start;
|
|
}
|
|
|
|
void __init pci_map_io_early(unsigned long pfn)
|
|
{
|
|
struct map_desc pci_io_desc = {
|
|
.virtual = PCI_IO_VIRT_BASE,
|
|
.type = MT_DEVICE,
|
|
.length = SZ_64K,
|
|
};
|
|
|
|
pci_io_desc.pfn = pfn;
|
|
iotable_init(&pci_io_desc, 1);
|
|
}
|