283 lines
8.2 KiB
C
283 lines
8.2 KiB
C
/*
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* linux/arch/arm/mach-omap1/timer32k.c
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*
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* OMAP 32K Timer
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*
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* Copyright (C) 2004 - 2005 Nokia Corporation
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* Partial timer rewrite and additional dynamic tick timer support by
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* Tony Lindgen <tony@atomide.com> and
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* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* OMAP Dual-mode timer framework support by Timo Teras
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*
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* MPU timer code based on the older MPU timer code for OMAP
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* Copyright (C) 2000 RidgeRun, Inc.
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* Author: Greg Lonnon <glonnon@ridgerun.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/sched_clock.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include "hardware.h"
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#include "common.h"
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/*
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* ---------------------------------------------------------------------------
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* 32KHz OS timer
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*
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* This currently works only on 16xx, as 1510 does not have the continuous
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* 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
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* of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
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* on 1510 would be possible, but the timer would not be as accurate as
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* with the 32KHz synchronized timer.
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* ---------------------------------------------------------------------------
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*/
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/* 16xx specific defines */
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#define OMAP1_32K_TIMER_BASE 0xfffb9000
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#define OMAP1_32KSYNC_TIMER_BASE 0xfffbc400
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#define OMAP1_32K_TIMER_CR 0x08
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#define OMAP1_32K_TIMER_TVR 0x00
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#define OMAP1_32K_TIMER_TCR 0x04
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#define OMAP_32K_TICKS_PER_SEC (32768)
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/*
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* TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
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* so with HZ = 128, TVR = 255.
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*/
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#define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
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#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
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(((nr_jiffies) * (clock_rate)) / HZ)
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static inline void omap_32k_timer_write(int val, int reg)
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{
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omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
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}
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static inline void omap_32k_timer_start(unsigned long load_val)
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{
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if (!load_val)
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load_val = 1;
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omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
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omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
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}
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static inline void omap_32k_timer_stop(void)
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{
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omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
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}
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#define omap_32k_timer_ack_irq()
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static int omap_32k_timer_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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omap_32k_timer_start(delta);
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return 0;
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}
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static int omap_32k_timer_shutdown(struct clock_event_device *evt)
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{
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omap_32k_timer_stop();
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return 0;
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}
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static int omap_32k_timer_set_periodic(struct clock_event_device *evt)
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{
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omap_32k_timer_stop();
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omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
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return 0;
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}
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static struct clock_event_device clockevent_32k_timer = {
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.name = "32k-timer",
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = omap_32k_timer_set_next_event,
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.set_state_shutdown = omap_32k_timer_shutdown,
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.set_state_periodic = omap_32k_timer_set_periodic,
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.set_state_oneshot = omap_32k_timer_shutdown,
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.tick_resume = omap_32k_timer_shutdown,
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};
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static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_32k_timer;
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omap_32k_timer_ack_irq();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static __init void omap_init_32k_timer(void)
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{
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if (request_irq(INT_OS_TIMER, omap_32k_timer_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL))
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pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER);
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clockevent_32k_timer.cpumask = cpumask_of(0);
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clockevents_config_and_register(&clockevent_32k_timer,
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OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe);
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}
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/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
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#define OMAP2_32KSYNCNT_REV_OFF 0x0
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#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
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#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
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#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
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/*
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* 32KHz clocksource ... always available, on pretty most chips except
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* OMAP 730 and 1510. Other timers could be used as clocksources, with
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* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
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* but systems won't necessarily want to spend resources that way.
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*/
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static void __iomem *sync32k_cnt_reg;
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static u64 notrace omap_32k_read_sched_clock(void)
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{
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return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
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}
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/**
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* omap_read_persistent_clock64 - Return time from a persistent clock.
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*
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* Reads the time from a source which isn't disabled during PM, the
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* 32k sync timer. Convert the cycles elapsed since last read into
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* nsecs and adds to a monotonically increasing timespec64.
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*/
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static struct timespec64 persistent_ts;
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static cycles_t cycles;
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static unsigned int persistent_mult, persistent_shift;
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static void omap_read_persistent_clock64(struct timespec64 *ts)
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{
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unsigned long long nsecs;
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cycles_t last_cycles;
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last_cycles = cycles;
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cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
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nsecs = clocksource_cyc2ns(cycles - last_cycles,
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persistent_mult, persistent_shift);
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timespec64_add_ns(&persistent_ts, nsecs);
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*ts = persistent_ts;
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}
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/**
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* omap_init_clocksource_32k - setup and register counter 32k as a
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* kernel clocksource
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* @pbase: base addr of counter_32k module
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* @size: size of counter_32k to map
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*
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* Returns 0 upon success or negative error code upon failure.
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*
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*/
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static int __init omap_init_clocksource_32k(void __iomem *vbase)
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{
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int ret;
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/*
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* 32k sync Counter IP register offsets vary between the
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* highlander version and the legacy ones.
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* The 'SCHEME' bits(30-31) of the revision register is used
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* to identify the version.
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*/
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if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &
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OMAP2_32KSYNCNT_REV_SCHEME)
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sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
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else
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sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
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/*
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* 120000 rough estimate from the calculations in
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* __clocksource_update_freq_scale.
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*/
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clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
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32768, NSEC_PER_SEC, 120000);
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ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
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250, 32, clocksource_mmio_readl_up);
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if (ret) {
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pr_err("32k_counter: can't register clocksource\n");
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return ret;
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}
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sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
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register_persistent_clock(omap_read_persistent_clock64);
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pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
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return 0;
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}
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/*
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* ---------------------------------------------------------------------------
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* Timer initialization
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* ---------------------------------------------------------------------------
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*/
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int __init omap_32k_timer_init(void)
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{
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int ret = -ENODEV;
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if (cpu_is_omap16xx()) {
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void __iomem *base;
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struct clk *sync32k_ick;
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base = ioremap(OMAP1_32KSYNC_TIMER_BASE, SZ_1K);
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if (!base) {
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pr_err("32k_counter: failed to map base addr\n");
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return -ENODEV;
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}
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sync32k_ick = clk_get(NULL, "omap_32ksync_ick");
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if (!IS_ERR(sync32k_ick))
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clk_prepare_enable(sync32k_ick);
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ret = omap_init_clocksource_32k(base);
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}
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if (!ret)
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omap_init_32k_timer();
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return ret;
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}
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