93 lines
3.9 KiB
C
93 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* AM33XX CM offset macros
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*
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
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#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
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#include "cm.h"
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#include "cm-regbits-33xx.h"
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#include "prcm-common.h"
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/* CM base address */
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#define AM33XX_CM_BASE 0x44e00000
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#define AM33XX_CM_REGADDR(inst, reg) \
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AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
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/* CM instances */
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#define AM33XX_CM_PER_MOD 0x0000
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#define AM33XX_CM_WKUP_MOD 0x0400
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#define AM33XX_CM_DPLL_MOD 0x0500
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#define AM33XX_CM_MPU_MOD 0x0600
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#define AM33XX_CM_DEVICE_MOD 0x0700
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#define AM33XX_CM_RTC_MOD 0x0800
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#define AM33XX_CM_GFX_MOD 0x0900
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#define AM33XX_CM_CEFUSE_MOD 0x0A00
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/* CM.PER_CM register offsets */
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#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
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#define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
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#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004
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#define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
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#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008
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#define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
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#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c
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#define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
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#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028
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#define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
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#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c
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#define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
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#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c
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#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
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#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140
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#define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
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#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144
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#define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
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#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148
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#define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
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#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150
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#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
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/* CM.WKUP_CM register offsets */
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#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
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#define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
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#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018
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#define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
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#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc
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#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
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/* CM.DPLL_CM register offsets */
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#define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
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/* CM.MPU_CM register offsets */
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#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
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#define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
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#define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
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/* CM.DEVICE_CM register offsets */
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/* CM.RTC_CM register offsets */
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#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004
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#define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
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/* CM.GFX_CM register offsets */
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#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000
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#define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
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#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c
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#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
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/* CM.CEFUSE_CM register offsets */
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#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
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#define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
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#ifndef __ASSEMBLER__
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int am33xx_cm_init(const struct omap_prcm_init_data *data);
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#endif /* ASSEMBLER */
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#endif
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