348 lines
9.0 KiB
Plaintext
348 lines
9.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright 2019-2021 TQ-Systems GmbH
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*/
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/dts-v1/;
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#include "imx8mq-tqma8mq.dtsi"
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#include "mba8mx.dtsi"
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/ {
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model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";
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compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";
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aliases {
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eeprom0 = &eeprom3;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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rtc0 = &pcf85063;
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rtc1 = &snvs_rtc;
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};
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extcon_usbotg: extcon-usbotg0 {
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compatible = "linux,extcon-usb-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbcon0>;
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id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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};
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pcie0_refclk: pcie0-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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pcie1_refclk: pcie1-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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reg_otg_vbus: regulator-otg-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_regotgvbus>;
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regulator-name = "MBA8MQ_OTG_VBUS";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&btn2 {
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gpios = <&gpio3 17 GPIO_ACTIVE_LOW>;
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};
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&gpio_leds {
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led3 {
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label = "led3";
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gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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};
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};
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&i2c1 {
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expander2: gpio@25 {
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compatible = "nxp,pca9555";
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reg = <0x25>;
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gpio-controller;
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#gpio-cells = <2>;
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vcc-supply = <®_vcc_3v3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_expander>;
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interrupt-parent = <&gpio1>;
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interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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mpcie-rst-hog {
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gpio-hog;
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gpios = <13 0>;
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output-high;
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line-name = "MPCIE_RST#";
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};
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};
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};
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&irqsteer {
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status = "okay";
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};
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&led2 {
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gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
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};
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&pcie0 {
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reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
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clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
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<&pcie0_refclk>,
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<&clk IMX8MQ_CLK_PCIE1_PHY>,
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<&clk IMX8MQ_CLK_PCIE1_AUX>;
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epdev_on-supply = <®_vcc_3v3>;
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hard-wired = <1>;
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status = "okay";
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};
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/*
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* miniPCIe, also usable for cards with USB. Therefore configure the reset as
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* static gpio hog.
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*/
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&pcie1 {
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clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
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<&pcie1_refclk>,
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<&clk IMX8MQ_CLK_PCIE2_PHY>,
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<&clk IMX8MQ_CLK_PCIE2_AUX>;
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epdev_on-supply = <®_vcc_3v3>;
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hard-wired = <1>;
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status = "okay";
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};
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&sai3 {
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assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
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assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
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clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
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<&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
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<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
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<&clk IMX8MQ_AUDIO_PLL2_OUT>;
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};
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&tlv320aic3x04 {
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clock-names = "mclk";
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clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>;
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};
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&uart1 {
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assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
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};
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&uart2 {
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assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
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};
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/* console */
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&uart3 {
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assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
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assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
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};
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&usb3_phy0 {
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vbus-supply = <®_otg_vbus>;
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status = "okay";
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};
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&usb_dwc3_0 {
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/* we implement dual role but not full featured OTG */
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extcon = <&extcon_usbotg>;
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hnp-disable;
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srp-disable;
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adp-disable;
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/* OC not supported due to non matching active polarity */
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disable-over-current;
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dr_mode = "otg";
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status = "okay";
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};
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&usb3_phy1 {
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status = "okay";
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};
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&usb_dwc3_1 {
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status = "okay";
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dr_mode = "host";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x0000004e>,
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<MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x0000004e>,
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<MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x0000004e>,
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<MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0000004e>;
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};
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x0000004e>,
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<MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x0000004e>,
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<MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x0000004e>,
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<MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x0000004e>;
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};
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pinctrl_expander: expandergrp {
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fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0xd6>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
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<MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23>,
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<MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
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<MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
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<MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
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<MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
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<MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
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<MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
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<MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
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<MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
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<MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
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<MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
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<MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
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<MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>;
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};
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pinctrl_gpiobutton: gpiobuttongrp {
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fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41>,
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<MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41>,
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<MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41>;
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};
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pinctrl_gpioled: gpioledgrp {
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fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x41>,
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<MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41>,
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<MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067>,
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<MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067>;
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};
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pinctrl_i2c2_gpio: i2c2gpiogrp {
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fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x40000067>,
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<MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x40000067>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000067>,
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<MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000067>;
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};
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pinctrl_i2c3_gpio: i2c3gpiogrp {
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fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x40000067>,
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<MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x40000067>;
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};
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pinctrl_pwm3: pwm3grp {
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fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x16>;
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};
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pinctrl_pwm4: pwm4grp {
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fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x16>;
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};
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pinctrl_regotgvbus: reggotgvbusgrp {
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/* USB1 OTG PWR as GPIO */
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fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x06>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1>;
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};
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pinctrl_sai3: sai3grp {
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fsl,pins = <MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6>,
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<MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6>,
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<MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6>,
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<MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6>,
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<MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6>,
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<MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6>,
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<MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79>,
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<MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79>,
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<MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79>,
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<MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79>;
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};
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pinctrl_uart4: uart4grp {
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fsl,pins = <MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79>,
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<MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79>;
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};
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pinctrl_usbcon0: usb0congrp {
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/* ID: floating / high: device, low: host -> use PU */
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fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xe6>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83>,
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<MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3>,
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<MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3>,
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<MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3>,
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<MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3>,
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<MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3>,
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<MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85>,
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<MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5>,
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<MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5>,
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<MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5>,
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<MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5>,
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<MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5>,
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<MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f>,
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<MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7>,
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<MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7>,
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<MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7>,
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<MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7>,
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<MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7>,
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<MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>;
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};
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pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
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fsl,pins = <MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41>;
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};
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};
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