478 lines
12 KiB
Plaintext
478 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mediatek,mt6795-clk.h>
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#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
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#include <dt-bindings/reset/mediatek,mt6795-resets.h>
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/ {
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compatible = "mediatek,mt6795";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x000>;
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cci-control-port = <&cci_control2>;
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next-level-cache = <&l2_0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x001>;
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cci-control-port = <&cci_control2>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x002>;
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cci-control-port = <&cci_control2>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_0>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x003>;
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cci-control-port = <&cci_control2>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_0>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x100>;
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cci-control-port = <&cci_control1>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_1>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x101>;
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cci-control-port = <&cci_control1>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_1>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x102>;
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cci-control-port = <&cci_control1>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_1>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x103>;
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cci-control-port = <&cci_control1>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_1>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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l2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <1048576>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-unified;
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};
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l2_1: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <1048576>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-unified;
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};
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};
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clk26m: oscillator-26m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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clk32k: oscillator-32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "clk32k";
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt6795-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt6795-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt6795-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt6795-pinctrl";
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reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
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reg-names = "base", "eint";
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 196>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt6795-wdt";
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reg = <0 0x10007000 0 0x100>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
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#reset-cells = <1>;
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timeout-sec = <20>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt6795-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x1000>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&clk32k>;
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};
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sysirq: intpol-controller@10200620 {
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compatible = "mediatek,mt6795-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200620 0 0x20>;
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};
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systimer: timer@10200670 {
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compatible = "mediatek,mt6795-systimer";
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reg = <0 0x10200670 0 0x10>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&system_clk>;
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clock-names = "clk13m";
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};
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gic: interrupt-controller@10221000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x10221000 0 0x1000>,
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<0 0x10222000 0 0x2000>,
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<0 0x10224000 0 0x2000>,
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<0 0x10226000 0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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cci: cci@10390000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0 0x10390000 0 0x1000>;
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ranges = <0 0 0x10390000 0x10000>;
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cci_control0: slave-if@1000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace-lite";
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reg = <0x1000 0x1000>;
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};
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cci_control1: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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};
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cci_control2: slave-if@5000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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pmu@9000 {
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compatible = "arm,cci-400-pmu,r1";
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reg = <0x9000 0x5000>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt6795-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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dmas = <&apdma 0>, <&apdma 1>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt6795-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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dmas = <&apdma 2>, <&apdma 3>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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apdma: dma-controller@11000380 {
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compatible = "mediatek,mt6795-uart-dma",
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"mediatek,mt6577-uart-dma";
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reg = <0 0x11000380 0 0x60>,
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<0 0x11000400 0 0x60>,
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<0 0x11000480 0 0x60>,
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<0 0x11000500 0 0x60>,
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<0 0x11000580 0 0x60>,
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<0 0x11000600 0 0x60>,
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<0 0x11000680 0 0x60>,
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<0 0x11000700 0 0x60>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
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dma-requests = <8>;
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clocks = <&pericfg CLK_PERI_AP_DMA>;
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clock-names = "apdma";
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mediatek,dma-33bits;
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#dma-cells = <1>;
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt6795-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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dmas = <&apdma 4>, <&apdma 5>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt6795-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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dmas = <&apdma 6>, <&apdma 7>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt6795-mmc";
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reg = <0 0x11230000 0 0x1000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_0>,
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<&topckgen CLK_TOP_MSDC50_0_H_SEL>,
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<&topckgen CLK_TOP_MSDC50_0_SEL>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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mmc1: mmc@11240000 {
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compatible = "mediatek,mt6795-mmc";
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reg = <0 0x11240000 0 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_1>,
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<&topckgen CLK_TOP_AXI_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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mmc2: mmc@11250000 {
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compatible = "mediatek,mt6795-mmc";
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reg = <0 0x11250000 0 0x1000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_2>,
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<&topckgen CLK_TOP_AXI_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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mmc3: mmc@11260000 {
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compatible = "mediatek,mt6795-mmc";
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reg = <0 0x11260000 0 0x1000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_3>,
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<&topckgen CLK_TOP_AXI_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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};
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};
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