558 lines
15 KiB
Plaintext
558 lines
15 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7986-clk.h>
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#include <dt-bindings/reset/mt7986-resets.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "mediatek,mt7986a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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clk40m: oscillator-40m {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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clock-output-names = "clkxtal";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x0>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x2>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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#cooling-cells = <2>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x30000>;
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no-map;
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};
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wmcpu_emi: wmcpu-reserved@4fc00000 {
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no-map;
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reg = <0 0x4fc00000 0 0x00100000>;
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};
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wo_emi0: wo-emi@4fd00000 {
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reg = <0 0x4fd00000 0 0x40000>;
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no-map;
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};
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wo_emi1: wo-emi@4fd40000 {
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reg = <0 0x4fd40000 0 0x40000>;
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no-map;
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};
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wo_ilm0: wo-ilm@151e0000 {
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reg = <0 0x151e0000 0 0x8000>;
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no-map;
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};
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wo_ilm1: wo-ilm@151f0000 {
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reg = <0 0x151f0000 0 0x8000>;
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no-map;
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};
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wo_data: wo-data@4fd80000 {
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reg = <0 0x4fd80000 0 0x240000>;
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no-map;
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};
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wo_dlm0: wo-dlm@151e8000 {
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reg = <0 0x151e8000 0 0x2000>;
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no-map;
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};
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wo_dlm1: wo-dlm@151f8000 {
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reg = <0 0x151f8000 0 0x2000>;
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no-map;
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};
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wo_boot: wo-boot@15194000 {
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reg = <0 0x15194000 0 0x1000>;
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no-map;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x10000>, /* GICD */
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<0 0x0c080000 0 0x80000>, /* GICR */
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<0 0x0c400000 0 0x2000>, /* GICC */
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<0 0x0c410000 0 0x1000>, /* GICH */
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<0 0x0c420000 0 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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infracfg: infracfg@10001000 {
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compatible = "mediatek,mt7986-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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wed_pcie: wed-pcie@10003000 {
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compatible = "mediatek,mt7986-wed-pcie",
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"syscon";
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reg = <0 0x10003000 0 0x10>;
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};
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topckgen: topckgen@1001b000 {
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compatible = "mediatek,mt7986-topckgen", "syscon";
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reg = <0 0x1001B000 0 0x1000>;
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#clock-cells = <1>;
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7986-wdt";
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reg = <0 0x1001c000 0 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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status = "disabled";
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};
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apmixedsys: apmixedsys@1001e000 {
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compatible = "mediatek,mt7986-apmixedsys";
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reg = <0 0x1001E000 0 0x1000>;
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#clock-cells = <1>;
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};
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pio: pinctrl@1001f000 {
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compatible = "mediatek,mt7986a-pinctrl";
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reg = <0 0x1001f000 0 0x1000>,
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<0 0x11c30000 0 0x1000>,
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<0 0x11c40000 0 0x1000>,
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<0 0x11e20000 0 0x1000>,
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<0 0x11e30000 0 0x1000>,
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<0 0x11f00000 0 0x1000>,
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<0 0x11f10000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
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"iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 100>;
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interrupt-controller;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7986-sgmiisys_0",
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"syscon";
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reg = <0 0x10060000 0 0x1000>;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7986-sgmiisys_1",
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"syscon";
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reg = <0 0x10070000 0 0x1000>;
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#clock-cells = <1>;
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};
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trng: rng@1020f000 {
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compatible = "mediatek,mt7986-rng",
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"mediatek,mt7623-rng";
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reg = <0 0x1020f000 0 0x100>;
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clocks = <&infracfg CLK_INFRA_TRNG_CK>;
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clock-names = "rng";
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status = "disabled";
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};
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crypto: crypto@10320000 {
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compatible = "inside-secure,safexcel-eip97";
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reg = <0 0x10320000 0 0x40000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ring0", "ring1", "ring2", "ring3";
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clocks = <&infracfg CLK_INFRA_EIP97_CK>;
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clock-names = "infra_eip97_ck";
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assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
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assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_UART0_SEL>,
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<&infracfg CLK_INFRA_UART0_CK>;
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clock-names = "baud", "bus";
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_UART0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_UART1_SEL>,
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<&infracfg CLK_INFRA_UART1_CK>;
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clock-names = "baud", "bus";
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assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_UART2_SEL>,
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<&infracfg CLK_INFRA_UART2_CK>;
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clock-names = "baud", "bus";
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assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
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status = "disabled";
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};
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i2c0: i2c@11008000 {
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compatible = "mediatek,mt7986-i2c";
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reg = <0 0x11008000 0 0x90>,
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<0 0x10217080 0 0x80>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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clock-div = <5>;
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clocks = <&infracfg CLK_INFRA_I2C0_CK>,
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<&infracfg CLK_INFRA_AP_DMA_CK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_MPLL_D2>,
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<&topckgen CLK_TOP_SPI_SEL>,
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<&infracfg CLK_INFRA_SPI0_CK>,
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<&infracfg CLK_INFRA_SPI0_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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status = "disabled";
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};
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spi1: spi@1100b000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100b000 0 0x100>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_MPLL_D2>,
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<&topckgen CLK_TOP_SPIM_MST_SEL>,
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<&infracfg CLK_INFRA_SPI1_CK>,
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<&infracfg CLK_INFRA_SPI1_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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status = "disabled";
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};
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ssusb: usb@11200000 {
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compatible = "mediatek,mt7986-xhci",
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"mediatek,mtk-xhci";
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reg = <0 0x11200000 0 0x2e00>,
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<0 0x11203e00 0 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
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<&infracfg CLK_INFRA_IUSB_CK>,
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<&infracfg CLK_INFRA_IUSB_133_CK>,
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<&infracfg CLK_INFRA_IUSB_66M_CK>,
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<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
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clock-names = "sys_ck",
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"ref_ck",
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"mcu_ck",
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"dma_ck",
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"xhci_ck";
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phys = <&u2port0 PHY_TYPE_USB2>,
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<&u3port0 PHY_TYPE_USB3>,
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<&u2port1 PHY_TYPE_USB2>;
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7986-mmc";
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reg = <0 0x11230000 0 0x1000>,
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<0 0x11c20000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
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<&infracfg CLK_INFRA_MSDC_HCK_CK>,
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<&infracfg CLK_INFRA_MSDC_CK>,
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<&infracfg CLK_INFRA_MSDC_133M_CK>,
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<&infracfg CLK_INFRA_MSDC_66M_CK>;
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clock-names = "source", "hclk", "source_cg", "bus_clk",
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"sys_cg";
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status = "disabled";
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};
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pcie: pcie@11280000 {
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compatible = "mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x00 0x11280000 0x00 0x4000>;
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reg-names = "pcie-mac";
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0x00 0x20000000 0x00
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0x20000000 0x00 0x10000000>;
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clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
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<&infracfg CLK_INFRA_IPCIE_CK>,
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<&infracfg CLK_INFRA_IPCIER_CK>,
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<&infracfg CLK_INFRA_IPCIEB_CK>;
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clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
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status = "disabled";
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phys = <&pcie_port PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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pcie_intc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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pcie_phy: t-phy@11c00000 {
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compatible = "mediatek,mt7986-tphy",
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"mediatek,generic-tphy-v2";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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pcie_port: pcie-phy@11c00000 {
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reg = <0 0x11c00000 0 0x20000>;
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clocks = <&clk40m>;
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clock-names = "ref";
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#phy-cells = <1>;
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};
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};
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usb_phy: t-phy@11e10000 {
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compatible = "mediatek,mt7986-tphy",
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"mediatek,generic-tphy-v2";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x11e10000 0x1700>;
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status = "disabled";
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u2port0: usb-phy@0 {
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reg = <0x0 0x700>;
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clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
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<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
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clock-names = "ref", "da_ref";
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#phy-cells = <1>;
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};
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u3port0: usb-phy@700 {
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reg = <0x700 0x900>;
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clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
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clock-names = "ref";
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#phy-cells = <1>;
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};
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u2port1: usb-phy@1000 {
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reg = <0x1000 0x700>;
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clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
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<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
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clock-names = "ref", "da_ref";
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#phy-cells = <1>;
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};
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};
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ethsys: syscon@15000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7986-ethsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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wed0: wed@15010000 {
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compatible = "mediatek,mt7986-wed",
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"syscon";
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reg = <0 0x15010000 0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
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memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
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<&wo_data>, <&wo_boot>;
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memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
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"wo-data", "wo-boot";
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mediatek,wo-ccif = <&wo_ccif0>;
|
|
};
|
|
|
|
wed1: wed@15011000 {
|
|
compatible = "mediatek,mt7986-wed",
|
|
"syscon";
|
|
reg = <0 0x15011000 0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
|
memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
|
|
<&wo_data>, <&wo_boot>;
|
|
memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
|
|
"wo-data", "wo-boot";
|
|
mediatek,wo-ccif = <&wo_ccif1>;
|
|
};
|
|
|
|
wo_ccif0: syscon@151a5000 {
|
|
compatible = "mediatek,mt7986-wo-ccif", "syscon";
|
|
reg = <0 0x151a5000 0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
wo_ccif1: syscon@151ad000 {
|
|
compatible = "mediatek,mt7986-wo-ccif", "syscon";
|
|
reg = <0 0x151ad000 0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
eth: ethernet@15100000 {
|
|
compatible = "mediatek,mt7986-eth";
|
|
reg = <0 0x15100000 0 0x80000>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <ðsys CLK_ETH_FE_EN>,
|
|
<ðsys CLK_ETH_GP2_EN>,
|
|
<ðsys CLK_ETH_GP1_EN>,
|
|
<ðsys CLK_ETH_WOCPU1_EN>,
|
|
<ðsys CLK_ETH_WOCPU0_EN>,
|
|
<&sgmiisys0 CLK_SGMII0_TX250M_EN>,
|
|
<&sgmiisys0 CLK_SGMII0_RX250M_EN>,
|
|
<&sgmiisys0 CLK_SGMII0_CDR_REF>,
|
|
<&sgmiisys0 CLK_SGMII0_CDR_FB>,
|
|
<&sgmiisys1 CLK_SGMII1_TX250M_EN>,
|
|
<&sgmiisys1 CLK_SGMII1_RX250M_EN>,
|
|
<&sgmiisys1 CLK_SGMII1_CDR_REF>,
|
|
<&sgmiisys1 CLK_SGMII1_CDR_FB>,
|
|
<&topckgen CLK_TOP_NETSYS_SEL>,
|
|
<&topckgen CLK_TOP_NETSYS_500M_SEL>;
|
|
clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
|
|
"sgmii_tx250m", "sgmii_rx250m",
|
|
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
|
"sgmii2_tx250m", "sgmii2_rx250m",
|
|
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
|
"netsys0", "netsys1";
|
|
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
|
|
<&topckgen CLK_TOP_SGM_325M_SEL>;
|
|
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
|
|
<&apmixedsys CLK_APMIXED_SGMPLL>;
|
|
mediatek,ethsys = <ðsys>;
|
|
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
|
mediatek,wed-pcie = <&wed_pcie>;
|
|
mediatek,wed = <&wed0>, <&wed1>;
|
|
#reset-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wifi: wifi@18000000 {
|
|
compatible = "mediatek,mt7986-wmac";
|
|
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
|
|
reset-names = "consys";
|
|
clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
|
|
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
|
|
clock-names = "mcu", "ap2conn";
|
|
reg = <0 0x18000000 0 0x1000000>,
|
|
<0 0x10003000 0 0x1000>,
|
|
<0 0x11d10000 0 0x1000>;
|
|
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
|
memory-region = <&wmcpu_emi>;
|
|
};
|
|
};
|
|
|
|
};
|