818 lines
20 KiB
Plaintext
818 lines
20 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* IPQ6018 SoC device tree source
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*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
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#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
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#include <dt-bindings/clock/qcom,apss-ipq.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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clocks {
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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xo: xo {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu_opp_table>;
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cpu-supply = <&ipq6018_s2>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu_opp_table>;
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cpu-supply = <&ipq6018_s2>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x2>;
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next-level-cache = <&L2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu_opp_table>;
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cpu-supply = <&ipq6018_s2>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x3>;
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next-level-cache = <&L2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu_opp_table>;
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cpu-supply = <&ipq6018_s2>;
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};
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <0x2>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq6018", "qcom,scm";
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};
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};
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cpu_opp_table: opp-table-cpu {
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compatible = "operating-points-v2";
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opp-shared;
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opp-864000000 {
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opp-hz = /bits/ 64 <864000000>;
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opp-microvolt = <725000>;
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clock-latency-ns = <200000>;
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};
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <787500>;
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clock-latency-ns = <200000>;
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};
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opp-1320000000 {
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opp-hz = /bits/ 64 <1320000000>;
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opp-microvolt = <862500>;
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clock-latency-ns = <200000>;
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};
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opp-1440000000 {
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opp-hz = /bits/ 64 <1440000000>;
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opp-microvolt = <925000>;
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clock-latency-ns = <200000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <987500>;
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clock-latency-ns = <200000>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1062500>;
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clock-latency-ns = <200000>;
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};
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};
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pmuv8: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rpm_msg_ram: memory@60000 {
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reg = <0x0 0x00060000 0x0 0x6000>;
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no-map;
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};
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tz: memory@4a600000 {
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reg = <0x0 0x4a600000 0x0 0x00400000>;
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no-map;
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};
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smem_region: memory@4aa00000 {
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reg = <0x0 0x4aa00000 0x0 0x00100000>;
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no-map;
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};
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q6_region: memory@4ab00000 {
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reg = <0x0 0x4ab00000 0x0 0x05500000>;
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no-map;
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};
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&apcs_glb 0>;
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rpm_requests: rpm-requests {
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compatible = "qcom,rpm-ipq6018";
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qcom,glink-channels = "rpm_requests";
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regulators {
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compatible = "qcom,rpm-mp5496-regulators";
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ipq6018_s2: s2 {
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regulator-min-microvolt = <725000>;
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regulator-max-microvolt = <1062500>;
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regulator-always-on;
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};
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};
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_region>;
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hwlocks = <&tcsr_mutex 0>;
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};
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soc: soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x0 0xffffffff>;
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dma-ranges;
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compatible = "simple-bus";
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qusb_phy_1: qusb@59000 {
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compatible = "qcom,ipq6018-qusb2-phy";
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reg = <0x0 0x00059000 0x0 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
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<&xo>;
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clock-names = "cfg_ahb", "ref";
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resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
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status = "disabled";
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};
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ssphy_0: ssphy@78000 {
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compatible = "qcom,ipq6018-qmp-usb3-phy";
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reg = <0x0 0x00078000 0x0 0x1c4>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc GCC_USB0_AUX_CLK>,
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<&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
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clock-names = "aux", "cfg_ahb", "ref";
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resets = <&gcc GCC_USB0_PHY_BCR>,
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<&gcc GCC_USB3PHY_0_PHY_BCR>;
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reset-names = "phy","common";
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status = "disabled";
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usb0_ssphy: phy@78200 {
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reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
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<0x0 0x00078400 0x0 0x200>, /* Rx */
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<0x0 0x00078800 0x0 0x1f8>, /* PCS */
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<0x0 0x00078600 0x0 0x044>; /* PCS misc */
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_USB0_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "gcc_usb0_pipe_clk_src";
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};
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};
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qusb_phy_0: qusb@79000 {
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compatible = "qcom,ipq6018-qusb2-phy";
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reg = <0x0 0x00079000 0x0 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
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<&xo>;
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clock-names = "cfg_ahb", "ref";
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resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
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status = "disabled";
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};
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pcie_phy: phy@84000 {
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compatible = "qcom,ipq6018-qmp-pcie-phy";
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reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
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status = "disabled";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc GCC_PCIE0_AUX_CLK>,
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<&gcc GCC_PCIE0_AHB_CLK>;
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clock-names = "aux", "cfg_ahb";
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
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<&gcc GCC_PCIE0PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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pcie_phy0: phy@84200 {
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reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
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<0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
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<0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
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<0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "gcc_pcie0_pipe_clk_src";
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#clock-cells = <0>;
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};
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};
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mdio: mdio@90000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
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reg = <0x0 0x00090000 0x0 0x64>;
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clocks = <&gcc GCC_MDIO_AHB_CLK>;
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clock-names = "gcc_mdio_ahb_clk";
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status = "disabled";
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};
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prng: qrng@e1000 {
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compatible = "qcom,prng-ee";
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reg = <0x0 0x000e3000 0x0 0x1000>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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cryptobam: dma-controller@704000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x0 0x00704000 0x0 0x20000>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <1>;
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qcom,controlled-remotely;
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};
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crypto: crypto@73a000 {
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compatible = "qcom,crypto-v5.1";
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reg = <0x0 0x0073a000 0x0 0x6000>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
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<&gcc GCC_CRYPTO_AXI_CLK>,
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<&gcc GCC_CRYPTO_CLK>;
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clock-names = "iface", "bus", "core";
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dmas = <&cryptobam 2>, <&cryptobam 3>;
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dma-names = "rx", "tx";
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq6018-pinctrl";
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reg = <0x0 0x01000000 0x0 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 80>;
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interrupt-controller;
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#interrupt-cells = <2>;
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serial_3_pins: serial3-state {
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pins = "gpio44", "gpio45";
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function = "blsp2_uart";
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drive-strength = <8>;
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bias-pull-down;
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};
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qpic_pins: qpic-state {
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pins = "gpio1", "gpio3", "gpio4",
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"gpio5", "gpio6", "gpio7",
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"gpio8", "gpio10", "gpio11",
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"gpio12", "gpio13", "gpio14",
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"gpio15", "gpio17";
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function = "qpic_pad";
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drive-strength = <8>;
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bias-disable;
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};
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};
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gcc: gcc@1800000 {
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compatible = "qcom,gcc-ipq6018";
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reg = <0x0 0x01800000 0x0 0x80000>;
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clocks = <&xo>, <&sleep_clk>;
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clock-names = "xo", "sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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tcsr_mutex: hwlock@1905000 {
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compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
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reg = <0x0 0x01905000 0x0 0x1000>;
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#hwlock-cells = <1>;
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};
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tcsr: syscon@1937000 {
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compatible = "qcom,tcsr-ipq6018", "syscon";
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reg = <0x0 0x01937000 0x0 0x21000>;
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};
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usb2: usb@70f8800 {
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compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
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reg = <0x0 0x070f8800 0x0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc GCC_USB1_MASTER_CLK>,
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<&gcc GCC_USB1_SLEEP_CLK>,
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<&gcc GCC_USB1_MOCK_UTMI_CLK>;
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clock-names = "core",
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"sleep",
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"mock_utmi";
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assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
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<&gcc GCC_USB1_MOCK_UTMI_CLK>;
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assigned-clock-rates = <133330000>,
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<24000000>;
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resets = <&gcc GCC_USB1_BCR>;
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status = "disabled";
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dwc_1: usb@7000000 {
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compatible = "snps,dwc3";
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reg = <0x0 0x07000000 0x0 0xcd00>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&qusb_phy_1>;
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phy-names = "usb2-phy";
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tx-fifo-resize;
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snps,is-utmi-l1-suspend;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,dis_u2_susphy_quirk;
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snps,dis_u3_susphy_quirk;
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dr_mode = "host";
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};
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};
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blsp_dma: dma-controller@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x0 0x07884000 0x0 0x2b000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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blsp1_uart3: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x0 0x078b1000 0x0 0x200>;
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interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_spi1: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x078b5000 0x0 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 12>, <&blsp_dma 13>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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blsp1_spi2: spi@78b6000 {
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x078b6000 0x0 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 14>, <&blsp_dma 15>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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blsp1_i2c2: i2c@78b6000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x078b6000 0x0 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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dmas = <&blsp_dma 14>, <&blsp_dma 15>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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blsp1_i2c3: i2c@78b7000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x078b7000 0x0 0x600>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
qpic_bam: dma-controller@7984000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0x0 0x07984000 0x0 0x1a000>;
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QPIC_AHB_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,ee = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qpic_nand: nand-controller@79b0000 {
|
|
compatible = "qcom,ipq6018-nand";
|
|
reg = <0x0 0x079b0000 0x0 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&gcc GCC_QPIC_CLK>,
|
|
<&gcc GCC_QPIC_AHB_CLK>;
|
|
clock-names = "core", "aon";
|
|
|
|
dmas = <&qpic_bam 0>,
|
|
<&qpic_bam 1>,
|
|
<&qpic_bam 2>;
|
|
dma-names = "tx", "rx", "cmd";
|
|
pinctrl-0 = <&qpic_pins>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3: usb@8af8800 {
|
|
compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
|
|
reg = <0x0 0x08af8800 0x0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
|
|
<&gcc GCC_USB0_MASTER_CLK>,
|
|
<&gcc GCC_USB0_SLEEP_CLK>,
|
|
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc",
|
|
"core",
|
|
"sleep",
|
|
"mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
|
|
<&gcc GCC_USB0_MASTER_CLK>,
|
|
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
|
|
assigned-clock-rates = <133330000>,
|
|
<133330000>,
|
|
<20000000>;
|
|
|
|
resets = <&gcc GCC_USB0_BCR>;
|
|
status = "disabled";
|
|
|
|
dwc_0: usb@8a00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x08a00000 0x0 0xcd00>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&qusb_phy_0>, <&usb0_ssphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
clocks = <&xo>;
|
|
clock-names = "ref";
|
|
tx-fifo-resize;
|
|
snps,is-utmi-l1-suspend;
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_u3_susphy_quirk;
|
|
dr_mode = "host";
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@b000000 {
|
|
compatible = "qcom,msm-qgic2";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x3>;
|
|
reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
|
|
<0x0 0x0b002000 0x0 0x1000>, /*GICC*/
|
|
<0x0 0x0b001000 0x0 0x1000>, /*GICH*/
|
|
<0x0 0x0b004000 0x0 0x1000>; /*GICV*/
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
ranges = <0 0 0 0xb00a000 0 0xffd>;
|
|
|
|
v2m@0 {
|
|
compatible = "arm,gic-v2m-frame";
|
|
msi-controller;
|
|
reg = <0x0 0x0 0x0 0xffd>;
|
|
};
|
|
};
|
|
|
|
watchdog@b017000 {
|
|
compatible = "qcom,kpss-wdt";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
|
|
reg = <0x0 0x0b017000 0x0 0x40>;
|
|
clocks = <&sleep_clk>;
|
|
timeout-sec = <10>;
|
|
};
|
|
|
|
apcs_glb: mailbox@b111000 {
|
|
compatible = "qcom,ipq6018-apcs-apps-global";
|
|
reg = <0x0 0x0b111000 0x0 0x1000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&a53pll>, <&xo>;
|
|
clock-names = "pll", "xo";
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
a53pll: clock@b116000 {
|
|
compatible = "qcom,ipq6018-a53pll";
|
|
reg = <0x0 0x0b116000 0x0 0x40>;
|
|
#clock-cells = <0>;
|
|
clocks = <&xo>;
|
|
clock-names = "xo";
|
|
};
|
|
|
|
timer@b120000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0x10000000>;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x0 0x0b120000 0x0 0x1000>;
|
|
|
|
frame@b120000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b121000 0x1000>,
|
|
<0x0b122000 0x1000>;
|
|
};
|
|
|
|
frame@b123000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b123000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b124000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b124000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b125000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b125000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b126000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b126000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b127000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b127000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b128000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b128000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
q6v5_wcss: remoteproc@cd00000 {
|
|
compatible = "qcom,ipq6018-wcss-pil";
|
|
reg = <0x0 0x0cd00000 0x0 0x4040>,
|
|
<0x0 0x004ab000 0x0 0x20>;
|
|
reg-names = "qdsp6",
|
|
"rmb";
|
|
interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
|
|
<&wcss_smp2p_in 0 0>,
|
|
<&wcss_smp2p_in 1 0>,
|
|
<&wcss_smp2p_in 2 0>,
|
|
<&wcss_smp2p_in 3 0>;
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"ready",
|
|
"handover",
|
|
"stop-ack";
|
|
|
|
resets = <&gcc GCC_WCSSAON_RESET>,
|
|
<&gcc GCC_WCSS_BCR>,
|
|
<&gcc GCC_WCSS_Q6_BCR>;
|
|
|
|
reset-names = "wcss_aon_reset",
|
|
"wcss_reset",
|
|
"wcss_q6_reset";
|
|
|
|
clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
|
clock-names = "prng";
|
|
|
|
qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
|
|
|
|
qcom,smem-states = <&wcss_smp2p_out 0>,
|
|
<&wcss_smp2p_out 1>;
|
|
qcom,smem-state-names = "shutdown",
|
|
"stop";
|
|
|
|
memory-region = <&q6_region>;
|
|
|
|
glink-edge {
|
|
interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
|
|
label = "rtr";
|
|
qcom,remote-pid = <1>;
|
|
mboxes = <&apcs_glb 8>;
|
|
|
|
qrtr_requests {
|
|
qcom,glink-channels = "IPCRTR";
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie0: pci@20000000 {
|
|
compatible = "qcom,pcie-ipq6018";
|
|
reg = <0x0 0x20000000 0x0 0xf1d>,
|
|
<0x0 0x20000f20 0x0 0xa8>,
|
|
<0x0 0x20001000 0x0 0x1000>,
|
|
<0x0 0x80000 0x0 0x4000>,
|
|
<0x0 0x20100000 0x0 0x1000>;
|
|
reg-names = "dbi", "elbi", "atu", "parf", "config";
|
|
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
max-link-speed = <3>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
phys = <&pcie_phy0>;
|
|
phy-names = "pciephy";
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
|
|
<0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
|
|
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_M_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_S_CLK>,
|
|
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
|
|
<&gcc PCIE0_RCHNG_CLK>;
|
|
clock-names = "iface",
|
|
"axi_m",
|
|
"axi_s",
|
|
"axi_bridge",
|
|
"rchng";
|
|
|
|
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
|
|
<&gcc GCC_PCIE0_SLEEP_ARES>,
|
|
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
|
|
<&gcc GCC_PCIE0_AHB_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
|
|
<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
|
|
reset-names = "pipe",
|
|
"sleep",
|
|
"sticky",
|
|
"axi_m",
|
|
"axi_s",
|
|
"ahb",
|
|
"axi_m_sticky",
|
|
"axi_s_sticky";
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
wcss: wcss-smp2p {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&apcs_glb 9>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
wcss_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
wcss_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
};
|