188 lines
3.0 KiB
Plaintext
188 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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*
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* This file defines the common audio settings for the child boards
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* using rt5682 codec and having 3 dmics connected to sc7280.
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*
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* Copyright 2022 Google LLC.
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*/
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/ {
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/* BOARD-SPECIFIC TOP LEVEL NODES */
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sound: sound {
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compatible = "google,sc7280-herobrine";
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model = "sc7280-rt5682-max98360a-3mic";
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audio-routing = "VA DMIC0", "vdd-micb",
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"VA DMIC1", "vdd-micb",
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"VA DMIC2", "vdd-micb",
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"VA DMIC3", "vdd-micb",
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"Headphone Jack", "HPOL",
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"Headphone Jack", "HPOR";
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#address-cells = <1>;
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#size-cells = <0>;
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dai-link@0 {
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link-name = "MAX98360";
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reg = <0>;
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cpu {
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sound-dai = <&lpass_cpu MI2S_SECONDARY>;
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};
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codec {
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sound-dai = <&max98360a>;
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};
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};
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dai-link@1 {
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link-name = "DisplayPort";
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reg = <1>;
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cpu {
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sound-dai = <&lpass_cpu LPASS_DP_RX>;
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};
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codec {
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sound-dai = <&mdss_dp>;
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};
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};
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dai-link@2 {
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link-name = "ALC5682";
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reg = <2>;
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cpu {
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sound-dai = <&lpass_cpu MI2S_PRIMARY>;
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};
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codec {
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sound-dai = <&alc5682 0 /* aif1 */>;
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};
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};
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dai-link@4 {
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link-name = "DMIC";
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reg = <4>;
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cpu {
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sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
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};
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codec {
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sound-dai = <&lpass_va_macro 0>;
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};
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};
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};
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};
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hp_i2c: &i2c2 {
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clock-frequency = <400000>;
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status = "okay";
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alc5682: codec@1a {
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compatible = "realtek,rt5682s";
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reg = <0x1a>;
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pinctrl-names = "default";
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pinctrl-0 = <&hp_irq>;
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#sound-dai-cells = <1>;
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interrupt-parent = <&tlmm>;
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interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
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AVDD-supply = <&pp1800_alc5682>;
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MICVDD-supply = <&pp3300_codec>;
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realtek,dmic1-data-pin = <1>;
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realtek,dmic1-clk-pin = <2>;
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realtek,jd-src = <1>;
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realtek,dmic-clk-rate-hz = <2048000>;
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};
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};
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&lpass_cpu {
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pinctrl-names = "default";
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pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>,
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<&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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dai-link@0 {
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reg = <MI2S_PRIMARY>;
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qcom,playback-sd-lines = <1>;
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qcom,capture-sd-lines = <0>;
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};
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dai-link@1 {
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reg = <MI2S_SECONDARY>;
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qcom,playback-sd-lines = <0>;
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};
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dai-link@5 {
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reg = <LPASS_DP_RX>;
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};
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dai-link@25 {
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reg = <LPASS_CDC_DMA_VA_TX0>;
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};
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};
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&lpass_va_macro {
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vdd-micb-supply = <&pp1800_l2c>;
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pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>, <&lpass_dmic23_clk>,
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<&lpass_dmic23_data>;
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status = "okay";
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};
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/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
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&lpass_dmic01_clk {
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drive-strength = <8>;
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bias-disable;
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};
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&lpass_dmic01_data {
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bias-pull-down;
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};
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&lpass_dmic23_clk {
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drive-strength = <8>;
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bias-disable;
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};
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&lpass_dmic23_data {
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bias-pull-down;
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};
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&mi2s0_data0 {
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drive-strength = <6>;
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bias-disable;
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};
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&mi2s0_data1 {
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drive-strength = <6>;
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bias-disable;
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};
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&mi2s0_mclk {
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drive-strength = <6>;
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bias-disable;
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};
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&mi2s0_sclk {
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drive-strength = <6>;
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bias-disable;
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};
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&mi2s0_ws {
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drive-strength = <6>;
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bias-disable;
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};
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