1398 lines
36 KiB
Plaintext
1398 lines
36 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
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*/
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,sm6375-gcc.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks {
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xo_board_clk: xo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo660";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo660";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_100>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_100: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo660";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_200>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_200: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo660";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_300>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_300: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo660";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_400>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_400: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo660";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_500>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_500: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo660";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_600>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_600: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo660";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_700>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_700: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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idle-state-name = "silver-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <702>;
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exit-latency-us = <915>;
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min-residency-us = <4001>;
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local-timer-stop;
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};
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BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <526>;
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exit-latency-us = <1854>;
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min-residency-us = <5555>;
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local-timer-stop;
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};
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};
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domain-idle-states {
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "domain-idle-state";
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idle-state-name = "cluster-power-collapse";
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arm,psci-suspend-param = <0x41000044>;
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entry-latency-us = <2752>;
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exit-latency-us = <3048>;
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min-residency-us = <6118>;
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local-timer-stop;
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};
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-sm6375", "qcom,scm";
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clocks = <&rpmcc RPM_SMD_CE1_CLK>;
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clock-names = "core";
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#reset-cells = <1>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: power-domain-cpu0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD1: power-domain-cpu1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD2: power-domain-cpu2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD3: power-domain-cpu3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD4: power-domain-cpu4 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD5: power-domain-cpu5 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD6: power-domain-cpu6 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD7: power-domain-cpu7 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CLUSTER_PD: power-domain-cpu-cluster0 {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_SLEEP_0>;
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};
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};
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qup_opp_table: opp-table-qup {
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compatible = "operating-points-v2";
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opp-75000000 {
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opp-hz = /bits/ 64 <75000000>;
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required-opps = <&rpmpd_opp_low_svs>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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required-opps = <&rpmpd_opp_svs>;
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};
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opp-128000000 {
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opp-hz = /bits/ 64 <128000000>;
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required-opps = <&rpmpd_opp_nom>;
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};
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: hypervisor@80000000 {
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reg = <0 0x80000000 0 0x600000>;
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no-map;
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};
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xbl_aop_mem: xbl-aop@80700000 {
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reg = <0 0x80700000 0 0x100000>;
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no-map;
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};
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reserved_xbl_uefi: xbl-uefi-res@80880000 {
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reg = <0 0x80880000 0 0x14000>;
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no-map;
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};
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smem_mem: smem@80900000 {
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compatible = "qcom,smem";
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reg = <0 0x80900000 0 0x200000>;
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hwlocks = <&tcsr_mutex 3>;
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no-map;
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};
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fw_mem: fw@80b00000 {
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reg = <0 0x80b00000 0 0x100000>;
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no-map;
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};
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cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 {
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reg = <0 0x80c00000 0 0x1e00000>;
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no-map;
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};
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dfps_data_mem: dpfs-data@85e00000 {
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reg = <0 0x85e00000 0 0x100000>;
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no-map;
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};
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pil_wlan_mem: pil-wlan@86500000 {
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reg = <0 0x86500000 0 0x200000>;
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no-map;
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};
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pil_adsp_mem: pil-adsp@86700000 {
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reg = <0 0x86700000 0 0x2000000>;
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no-map;
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};
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pil_cdsp_mem: pil-cdsp@88700000 {
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reg = <0 0x88700000 0 0x1e00000>;
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no-map;
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};
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pil_video_mem: pil-video@8a500000 {
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reg = <0 0x8a500000 0 0x500000>;
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no-map;
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};
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pil_ipa_fw_mem: pil-ipa-fw@8aa00000 {
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reg = <0 0x8aa00000 0 0x10000>;
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no-map;
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};
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pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 {
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reg = <0 0x8aa10000 0 0xa000>;
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no-map;
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};
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pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 {
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reg = <0 0x8aa1a000 0 0x2000>;
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no-map;
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};
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pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 {
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reg = <0 0x8b800000 0 0x10000000>;
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no-map;
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};
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removed_mem: removed@c0000000 {
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reg = <0 0xc0000000 0 0x5100000>;
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no-map;
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};
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debug_mem: debug@ffb00000 {
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reg = <0 0xffb00000 0 0xc0000>;
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no-map;
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};
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last_log_mem: lastlog@ffbc0000 {
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reg = <0 0xffbc0000 0 0x80000>;
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no-map;
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};
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cmdline_region: cmdline@ffd00000 {
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reg = <0 0xffd00000 0 0x1000>;
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no-map;
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};
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts-extended = <&ipcc IPCC_CLIENT_AOP
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
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rpm_requests: rpm-requests {
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compatible = "qcom,rpm-sm6375";
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qcom,glink-channels = "rpm_requests";
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rpmcc: clock-controller {
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compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc";
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clocks = <&xo_board_clk>;
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clock-names = "xo";
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#clock-cells = <1>;
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};
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rpmpd: power-controller {
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compatible = "qcom,sm6375-rpmpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmpd_opp_table>;
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rpmpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmpd_opp_ret: opp1 {
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opp-level = <RPM_SMD_LEVEL_RETENTION>;
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};
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rpmpd_opp_min_svs: opp2 {
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opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
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};
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rpmpd_opp_low_svs: opp3 {
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opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
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};
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rpmpd_opp_svs: opp4 {
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opp-level = <RPM_SMD_LEVEL_SVS>;
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};
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rpmpd_opp_svs_plus: opp5 {
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opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
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};
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rpmpd_opp_nom: opp6 {
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opp-level = <RPM_SMD_LEVEL_NOM>;
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};
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rpmpd_opp_nom_plus: opp7 {
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opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
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};
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rpmpd_opp_turbo: opp8 {
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opp-level = <RPM_SMD_LEVEL_TURBO>;
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};
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rpmpd_opp_turbo_no_cpr: opp9 {
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opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
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};
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};
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};
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};
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};
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smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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smp2p_adsp_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_adsp_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-cdsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <94>, <432>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <5>;
|
|
|
|
smp2p_cdsp_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_cdsp_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
soc: soc@0 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0 0 0 0 0x10 0>;
|
|
dma-ranges = <0 0 0 0 0x10 0>;
|
|
compatible = "simple-bus";
|
|
|
|
ipcc: mailbox@208000 {
|
|
compatible = "qcom,sm6375-ipcc", "qcom,ipcc";
|
|
reg = <0 0x00208000 0 0x1000>;
|
|
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock@340000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
reg = <0x0 0x00340000 0x0 0x40000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
tlmm: pinctrl@500000 {
|
|
compatible = "qcom,sm6375-tlmm";
|
|
reg = <0 0x00500000 0 0x800000>;
|
|
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-ranges = <&tlmm 0 0 157>;
|
|
/* TODO: Hook up MPM as wakeup-parent when it's there */
|
|
interrupt-controller;
|
|
gpio-controller;
|
|
#interrupt-cells = <2>;
|
|
#gpio-cells = <2>;
|
|
|
|
sdc2_off_state: sdc2-off-state {
|
|
clk-pins {
|
|
pins = "sdc2_clk";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "sdc2_cmd";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "sdc2_data";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdc2_on_state: sdc2-on-state {
|
|
clk-pins {
|
|
pins = "sdc2_clk";
|
|
drive-strength = <16>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "sdc2_cmd";
|
|
drive-strength = <10>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "sdc2_data";
|
|
drive-strength = <10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qup_i2c0_default: qup-i2c0-default-state {
|
|
pins = "gpio0", "gpio1";
|
|
function = "qup00";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c1_default: qup-i2c1-default-state {
|
|
pins = "gpio61", "gpio62";
|
|
function = "qup01";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c2_default: qup-i2c2-default-state {
|
|
pins = "gpio45", "gpio46";
|
|
function = "qup02";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c8_default: qup-i2c8-default-state {
|
|
pins = "gpio19", "gpio20";
|
|
/* TLMM, GCC and vendor DT all have different indices.. */
|
|
function = "qup12";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c10_default: qup-i2c10-default-state {
|
|
pins = "gpio4", "gpio5";
|
|
function = "qup10";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi0_default: qup-spi0-default-state {
|
|
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
|
function = "qup00";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
gcc: clock-controller@1400000 {
|
|
compatible = "qcom,sm6375-gcc";
|
|
reg = <0 0x01400000 0 0x1f0000>;
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
|
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
|
|
<&sleep_clk>;
|
|
#power-domain-cells = <1>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
usb_1_hsphy: phy@162b000 {
|
|
compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";
|
|
reg = <0 0x0162b000 0 0x400>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
|
clock-names = "ref";
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spmi_bus: spmi@1c40000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0 0x01c40000 0 0x1100>,
|
|
<0 0x01e00000 0 0x2000000>,
|
|
<0 0x03e00000 0 0x100000>,
|
|
<0 0x03f00000 0 0xa0000>,
|
|
<0 0x01c0a000 0 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
};
|
|
|
|
rpm_msg_ram: sram@45f0000 {
|
|
compatible = "qcom,rpm-msg-ram";
|
|
reg = <0 0x045f0000 0 0x7000>;
|
|
};
|
|
|
|
sdhc_2: mmc@4784000 {
|
|
compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5";
|
|
reg = <0 0x04784000 0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>,
|
|
<&rpmcc RPM_SMD_XO_CLK_SRC>;
|
|
clock-names = "iface", "core", "xo";
|
|
resets = <&gcc GCC_SDCC2_BCR>;
|
|
iommus = <&apps_smmu 0x40 0x0>;
|
|
|
|
pinctrl-0 = <&sdc2_on_state>;
|
|
pinctrl-1 = <&sdc2_off_state>;
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
qcom,dll-config = <0x0007642c>;
|
|
qcom,ddr-config = <0x80040868>;
|
|
power-domains = <&rpmpd SM6375_VDDCX>;
|
|
operating-points-v2 = <&sdhc2_opp_table>;
|
|
bus-width = <4>;
|
|
|
|
status = "disabled";
|
|
|
|
sdhc2_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
required-opps = <&rpmpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-202000000 {
|
|
opp-hz = /bits/ 64 <202000000>;
|
|
required-opps = <&rpmpd_opp_svs_plus>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpi_dma0: dma-controller@4a00000 {
|
|
compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0 0x04a00000 0 0x60000>;
|
|
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-channels = <10>;
|
|
dma-channel-mask = <0x1f>;
|
|
iommus = <&apps_smmu 0x16 0x0>;
|
|
#dma-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_0: geniqup@4ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x04ac0000 0x0 0x2000>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x3 0x0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
i2c0: i2c@4a80000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x04a80000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
|
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c0_default>;
|
|
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@4a80000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x04a80000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
|
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_spi0_default>;
|
|
power-domains = <&rpmpd SM6375_VDDCX>;
|
|
operating-points-v2 = <&qup_opp_table>;
|
|
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@4a84000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x04a84000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
|
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c1_default>;
|
|
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@4a84000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x04a84000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
|
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmpd SM6375_VDDCX>;
|
|
operating-points-v2 = <&qup_opp_table>;
|
|
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@4a88000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x04a88000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
|
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c2_default>;
|
|
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@4a88000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x04a88000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
|
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmpd SM6375_VDDCX>;
|
|
operating-points-v2 = <&qup_opp_table>;
|
|
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/*
|
|
* As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream.
|
|
* There is a comment in the included DTSI of another SoC saying that they
|
|
* are not "bolled out" (probably meaning not routed to solder balls)
|
|
* TLMM driver however, suggests there are as many as 15 QUPs in total!
|
|
* Most of which don't even have pin configurations for.. Sad stuff!
|
|
*/
|
|
};
|
|
|
|
gpi_dma1: dma-controller@4c00000 {
|
|
compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0 0x04c00000 0 0x60000>;
|
|
interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-channels = <10>;
|
|
dma-channel-mask = <0x1f>;
|
|
iommus = <&apps_smmu 0xd6 0x0>;
|
|
#dma-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_1: geniqup@4cc0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x04cc0000 0x0 0x2000>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0xc3 0x0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
i2c6: i2c@4c80000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x04c80000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi6: spi@4c80000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x04c80000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmpd SM6375_VDDCX>;
|
|
operating-points-v2 = <&qup_opp_table>;
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@4c84000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x04c84000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi7: spi@4c84000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x04c84000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmpd SM6375_VDDCX>;
|
|
operating-points-v2 = <&qup_opp_table>;
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c8: i2c@4c88000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x04c88000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c8_default>;
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi8: spi@4c88000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x04c88000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmpd SM6375_VDDCX>;
|
|
operating-points-v2 = <&qup_opp_table>;
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c9: i2c@4c8c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x04c8c000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi9: spi@4c8c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x04c8c000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmpd SM6375_VDDCX>;
|
|
operating-points-v2 = <&qup_opp_table>;
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c10: i2c@4c90000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x04c90000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c10_default>;
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi10: spi@4c90000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x04c90000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmpd SM6375_VDDCX>;
|
|
operating-points-v2 = <&qup_opp_table>;
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usb_1: usb@4ef8800 {
|
|
compatible = "qcom,sm6375-dwc3", "qcom,dwc3";
|
|
reg = <0 0x04ef8800 0 0x400>;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
|
<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB3_PRIM_CLKREF_CLK>;
|
|
clock-names = "cfg_noc",
|
|
"core",
|
|
"iface",
|
|
"sleep",
|
|
"mock_utmi",
|
|
"xo";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <133333333>;
|
|
|
|
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hs_phy_irq",
|
|
"ss_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"dp_hs_phy_irq";
|
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>;
|
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
|
|
|
/*
|
|
* This property is there to allow USB2 to work, as
|
|
* USB3 is not implemented yet - (re)move it when
|
|
* proper support is in place.
|
|
*/
|
|
qcom,select-utmi-as-pipe-clk;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
usb_1_dwc3: usb@4e00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x04e00000 0 0xcd00>;
|
|
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
|
|
maximum-speed = "high-speed";
|
|
phys = <&usb_1_hsphy>;
|
|
phy-names = "usb2-phy";
|
|
iommus = <&apps_smmu 0xe0 0x0>;
|
|
|
|
/* Yes, this impl *does* have an unfunny number of quirks.. */
|
|
snps,hird-threshold = /bits/ 8 <0x10>;
|
|
snps,usb2-gadget-lpm-disable;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,is-utmi-l1-suspend;
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
snps,usb3_lpm_capable;
|
|
snps,has-lpm-erratum;
|
|
tx-fifo-resize;
|
|
};
|
|
};
|
|
|
|
remoteproc_adsp: remoteproc@a400000 {
|
|
compatible = "qcom,sm6375-adsp-pas";
|
|
reg = <0 0x0a400000 0 0x100>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmpd SM6375_VDD_LPI_CX>,
|
|
<&rpmpd SM6375_VDD_LPI_MX>;
|
|
power-domain-names = "lcx", "lmx";
|
|
|
|
memory-region = <&pil_adsp_mem>;
|
|
|
|
qcom,smem-states = <&smp2p_adsp_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
label = "lpass";
|
|
qcom,remote-pid = <2>;
|
|
};
|
|
};
|
|
|
|
remoteproc_cdsp: remoteproc@b000000 {
|
|
compatible = "qcom,sm6375-cdsp-pas";
|
|
reg = <0x0 0x0b000000 0x0 0x100000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmpd SM6375_VDDCX>;
|
|
power-domain-names = "cx";
|
|
|
|
memory-region = <&pil_cdsp_mem>;
|
|
|
|
qcom,smem-states = <&smp2p_cdsp_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
label = "cdsp";
|
|
qcom,remote-pid = <5>;
|
|
};
|
|
};
|
|
|
|
apps_smmu: iommu@c600000 {
|
|
compatible = "qcom,sm6375-smmu-500", "arm,mmu-500";
|
|
reg = <0 0x0c600000 0 0x100000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>,
|
|
<&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>,
|
|
<&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
|
|
#global-interrupts = <1>;
|
|
#iommu-cells = <2>;
|
|
};
|
|
|
|
intc: interrupt-controller@f200000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */
|
|
<0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */
|
|
interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
#redistributor-regions = <1>;
|
|
#interrupt-cells = <3>;
|
|
redistributor-stride = <0 0x20000>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
timer@f420000 {
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0 0x0f420000 0 0x1000>;
|
|
ranges = <0 0 0 0x20000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
frame@f421000 {
|
|
reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <0>;
|
|
};
|
|
|
|
frame@f423000 {
|
|
reg = <0x0f243000 0x1000>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f425000 {
|
|
reg = <0x0f425000 0x1000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f427000 {
|
|
reg = <0x0f427000 0x1000>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f429000 {
|
|
reg = <0x0f429000 0x1000>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f42b000 {
|
|
reg = <0x0f42b000 0x1000>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f42d000 {
|
|
reg = <0x0f42d000 0x1000>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <6>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@fd91000 {
|
|
compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
|
|
reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;
|
|
reg-names = "freq-domain0", "freq-domain1";
|
|
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
|
|
#freq-domain-cells = <1>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|