4159 lines
104 KiB
Plaintext
4159 lines
104 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2020, Linaro Limited
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*/
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#include <dt-bindings/interconnect/qcom,sm8350.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
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#include <dt-bindings/clock/qcom,gcc-sm8350.h>
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#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,sm8350.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/interconnect/qcom,sm8350.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_100>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_100: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_200>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_200: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_300>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_300: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_400>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_400: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_500>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_500: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_600>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_600: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_700>;
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qcom,freq-domain = <&cpufreq_hw 2>;
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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#cooling-cells = <2>;
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L2_700: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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idle-state-name = "silver-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <355>;
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exit-latency-us = <909>;
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min-residency-us = <3934>;
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local-timer-stop;
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};
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BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <241>;
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exit-latency-us = <1461>;
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min-residency-us = <4488>;
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local-timer-stop;
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};
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};
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domain-idle-states {
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "domain-idle-state";
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idle-state-name = "cluster-power-collapse";
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arm,psci-suspend-param = <0x4100c344>;
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entry-latency-us = <3263>;
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exit-latency-us = <6562>;
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min-residency-us = <9987>;
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local-timer-stop;
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};
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};
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};
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firmware {
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scm: scm {
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compatible = "qcom,scm-sm8350", "qcom,scm";
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#reset-cells = <1>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: power-domain-cpu0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD1: power-domain-cpu1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD2: power-domain-cpu2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD3: power-domain-cpu3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD4: power-domain-cpu4 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD5: power-domain-cpu5 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD6: power-domain-cpu6 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD7: power-domain-cpu7 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CLUSTER_PD: power-domain-cpu-cluster0 {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_SLEEP_0>;
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};
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};
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qup_opp_table_100mhz: opp-table-qup100mhz {
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compatible = "operating-points-v2";
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opp-50000000 {
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opp-hz = /bits/ 64 <50000000>;
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required-opps = <&rpmhpd_opp_min_svs>;
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};
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opp-75000000 {
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opp-hz = /bits/ 64 <75000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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};
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qup_opp_table_120mhz: opp-table-qup120mhz {
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compatible = "operating-points-v2";
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opp-50000000 {
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opp-hz = /bits/ 64 <50000000>;
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required-opps = <&rpmhpd_opp_min_svs>;
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};
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opp-75000000 {
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opp-hz = /bits/ 64 <75000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-120000000 {
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opp-hz = /bits/ 64 <120000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: memory@80000000 {
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reg = <0x0 0x80000000 0x0 0x600000>;
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no-map;
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};
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xbl_aop_mem: memory@80700000 {
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no-map;
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reg = <0x0 0x80700000 0x0 0x160000>;
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};
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cmd_db: memory@80860000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x80860000 0x0 0x20000>;
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no-map;
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};
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reserved_xbl_uefi_log: memory@80880000 {
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reg = <0x0 0x80880000 0x0 0x14000>;
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no-map;
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};
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smem@80900000 {
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compatible = "qcom,smem";
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reg = <0x0 0x80900000 0x0 0x200000>;
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hwlocks = <&tcsr_mutex 3>;
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no-map;
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};
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cpucp_fw_mem: memory@80b00000 {
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reg = <0x0 0x80b00000 0x0 0x100000>;
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no-map;
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};
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cdsp_secure_heap: memory@80c00000 {
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reg = <0x0 0x80c00000 0x0 0x4600000>;
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no-map;
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};
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pil_camera_mem: mmeory@85200000 {
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reg = <0x0 0x85200000 0x0 0x500000>;
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no-map;
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};
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pil_video_mem: memory@85700000 {
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reg = <0x0 0x85700000 0x0 0x500000>;
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no-map;
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};
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pil_cvp_mem: memory@85c00000 {
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reg = <0x0 0x85c00000 0x0 0x500000>;
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no-map;
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};
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pil_adsp_mem: memory@86100000 {
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reg = <0x0 0x86100000 0x0 0x2100000>;
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no-map;
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};
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pil_slpi_mem: memory@88200000 {
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reg = <0x0 0x88200000 0x0 0x1500000>;
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no-map;
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};
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pil_cdsp_mem: memory@89700000 {
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reg = <0x0 0x89700000 0x0 0x1e00000>;
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no-map;
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};
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pil_ipa_fw_mem: memory@8b500000 {
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reg = <0x0 0x8b500000 0x0 0x10000>;
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no-map;
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};
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pil_ipa_gsi_mem: memory@8b510000 {
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reg = <0x0 0x8b510000 0x0 0xa000>;
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no-map;
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};
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pil_gpu_mem: memory@8b51a000 {
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reg = <0x0 0x8b51a000 0x0 0x2000>;
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no-map;
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};
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pil_spss_mem: memory@8b600000 {
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reg = <0x0 0x8b600000 0x0 0x100000>;
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no-map;
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};
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pil_modem_mem: memory@8b800000 {
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reg = <0x0 0x8b800000 0x0 0x10000000>;
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no-map;
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};
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rmtfs_mem: memory@9b800000 {
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compatible = "qcom,rmtfs-mem";
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reg = <0x0 0x9b800000 0x0 0x280000>;
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no-map;
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qcom,client-id = <1>;
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qcom,vmid = <15>;
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};
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hyp_reserved_mem: memory@d0000000 {
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reg = <0x0 0xd0000000 0x0 0x800000>;
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no-map;
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};
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pil_trustedvm_mem: memory@d0800000 {
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reg = <0x0 0xd0800000 0x0 0x76f7000>;
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no-map;
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};
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qrtr_shbuf: memory@d7ef7000 {
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reg = <0x0 0xd7ef7000 0x0 0x9000>;
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no-map;
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};
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chan0_shbuf: memory@d7f00000 {
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reg = <0x0 0xd7f00000 0x0 0x80000>;
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no-map;
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};
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chan1_shbuf: memory@d7f80000 {
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reg = <0x0 0xd7f80000 0x0 0x80000>;
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no-map;
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};
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removed_mem: memory@d8800000 {
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reg = <0x0 0xd8800000 0x0 0x6800000>;
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no-map;
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};
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};
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smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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smp2p_adsp_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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|
|
smp2p_adsp_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-cdsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <94>, <432>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <5>;
|
|
|
|
smp2p_cdsp_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_cdsp_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
smp2p_modem_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_modem_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
ipa_smp2p_out: ipa-ap-to-modem {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
ipa_smp2p_in: ipa-modem-to-ap {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-slpi {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <481>, <430>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_SLPI
|
|
IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <3>;
|
|
|
|
smp2p_slpi_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_slpi_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
soc: soc@0 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0 0 0 0 0x10 0>;
|
|
dma-ranges = <0 0 0 0 0x10 0>;
|
|
compatible = "simple-bus";
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,gcc-sm8350";
|
|
reg = <0x0 0x00100000 0x0 0x1f0000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
clock-names = "bi_tcxo",
|
|
"sleep_clk",
|
|
"pcie_0_pipe_clk",
|
|
"pcie_1_pipe_clk",
|
|
"ufs_card_rx_symbol_0_clk",
|
|
"ufs_card_rx_symbol_1_clk",
|
|
"ufs_card_tx_symbol_0_clk",
|
|
"ufs_phy_rx_symbol_0_clk",
|
|
"ufs_phy_rx_symbol_1_clk",
|
|
"ufs_phy_tx_symbol_0_clk",
|
|
"usb3_phy_wrapper_gcc_usb30_pipe_clk",
|
|
"usb3_uni_phy_sec_gcc_usb30_pipe_clk";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&sleep_clk>,
|
|
<&pcie0_phy>,
|
|
<&pcie1_phy>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<&ufs_mem_phy_lanes 0>,
|
|
<&ufs_mem_phy_lanes 1>,
|
|
<&ufs_mem_phy_lanes 2>,
|
|
<0>,
|
|
<0>;
|
|
};
|
|
|
|
ipcc: mailbox@408000 {
|
|
compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
|
|
reg = <0 0x00408000 0 0x1000>;
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
gpi_dma2: dma-controller@800000 {
|
|
compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0 0x00800000 0 0x60000>;
|
|
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-channels = <12>;
|
|
dma-channel-mask = <0xff>;
|
|
iommus = <&apps_smmu 0x5f6 0x0>;
|
|
#dma-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_2: geniqup@8c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x008c0000 0x0 0x6000>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x5e3 0x0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
i2c14: i2c@880000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00880000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c14_default>;
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi14: spi@880000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00880000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c15: i2c@884000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00884000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c15_default>;
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi15: spi@884000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00884000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c16: i2c@888000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00888000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c16_default>;
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi16: spi@888000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00888000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c17: i2c@88c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x0088c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c17_default>;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi17: spi@88c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x0088c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* QUP no. 18 seems to be strictly SPI/UART-only */
|
|
|
|
spi18: spi@890000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00890000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart18: serial@890000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0 0x00890000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_uart18_default>;
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c19: i2c@894000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00894000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c19_default>;
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi19: spi@894000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00894000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpi_dma0: dma-controller@900000 {
|
|
compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0 0x09800000 0 0x60000>;
|
|
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-channels = <12>;
|
|
dma-channel-mask = <0x7e>;
|
|
iommus = <&apps_smmu 0x5b6 0x0>;
|
|
#dma-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_0: geniqup@9c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x009c0000 0x0 0x6000>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x5a3 0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
i2c0: i2c@980000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00980000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c0_default>;
|
|
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@980000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00980000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
|
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@984000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00984000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c1_default>;
|
|
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@984000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00984000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
|
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@988000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00988000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c2_default>;
|
|
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@988000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00988000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
|
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@98c000 {
|
|
compatible = "qcom,geni-debug-uart";
|
|
reg = <0 0x0098c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_uart3_default_state>;
|
|
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* QUP no. 3 seems to be strictly SPI-only */
|
|
|
|
spi3: spi@98c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x0098c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
|
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@990000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00990000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c4_default>;
|
|
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@990000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00990000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
|
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@994000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00994000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c5_default>;
|
|
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi5: spi@994000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00994000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
|
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@998000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00998000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c6_default>;
|
|
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi6: spi@998000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00998000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
|
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@998000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0 0x00998000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_uart6_default>;
|
|
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@99c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x0099c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c7_default>;
|
|
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi7: spi@99c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x0099c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
|
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
|
|
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpi_dma1: dma-controller@a00000 {
|
|
compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0 0x00a00000 0 0x60000>;
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-channels = <12>;
|
|
dma-channel-mask = <0xff>;
|
|
iommus = <&apps_smmu 0x56 0x0>;
|
|
#dma-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_1: geniqup@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x00ac0000 0x0 0x6000>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x43 0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
i2c8: i2c@a80000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a80000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c8_default>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi8: spi@a80000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a80000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_120mhz>;
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c9: i2c@a84000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a84000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c9_default>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi9: spi@a84000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a84000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c10: i2c@a88000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a88000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c10_default>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi10: spi@a88000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a88000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c11: i2c@a8c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a8c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c11_default>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi11: spi@a8c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a8c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c12: i2c@a90000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a90000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c12_default>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi12: spi@a90000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a90000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c13: i2c@a94000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a94000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c13_default>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi13: spi@a94000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0 0x00a94000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
rng: rng@10d3000 {
|
|
compatible = "qcom,prng-ee";
|
|
reg = <0 0x010d3000 0 0x1000>;
|
|
clocks = <&rpmhcc RPMH_HWKM_CLK>;
|
|
clock-names = "core";
|
|
};
|
|
|
|
config_noc: interconnect@1500000 {
|
|
compatible = "qcom,sm8350-config-noc";
|
|
reg = <0 0x01500000 0 0xa580>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mc_virt: interconnect@1580000 {
|
|
compatible = "qcom,sm8350-mc-virt";
|
|
reg = <0 0x01580000 0 0x1000>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
system_noc: interconnect@1680000 {
|
|
compatible = "qcom,sm8350-system-noc";
|
|
reg = <0 0x01680000 0 0x1c200>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
compatible = "qcom,sm8350-aggre1-noc";
|
|
reg = <0 0x016e0000 0 0x1f180>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
compatible = "qcom,sm8350-aggre2-noc";
|
|
reg = <0 0x01700000 0 0x33000>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1740000 {
|
|
compatible = "qcom,sm8350-mmss-noc";
|
|
reg = <0 0x01740000 0 0x1f080>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
pcie0: pci@1c00000 {
|
|
compatible = "qcom,pcie-sm8350";
|
|
reg = <0 0x01c00000 0 0x3000>,
|
|
<0 0x60000000 0 0xf1d>,
|
|
<0 0x60000f20 0 0xa8>,
|
|
<0 0x60001000 0 0x1000>,
|
|
<0 0x60100000 0 0x100000>;
|
|
reg-names = "parf", "dbi", "elbi", "atu", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
|
|
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
|
"msi4", "msi5", "msi6", "msi7";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
|
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
|
|
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
|
|
clock-names = "aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave",
|
|
"slave_q2a",
|
|
"tbu",
|
|
"ddrss_sf_tbu",
|
|
"aggre1",
|
|
"aggre0";
|
|
|
|
iommus = <&apps_smmu 0x1c00 0x7f>;
|
|
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
|
|
<0x100 &apps_smmu 0x1c01 0x1>;
|
|
|
|
resets = <&gcc GCC_PCIE_0_BCR>;
|
|
reset-names = "pci";
|
|
|
|
power-domains = <&gcc PCIE_0_GDSC>;
|
|
|
|
phys = <&pcie0_phy>;
|
|
phy-names = "pciephy";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie0_phy: phy@1c06000 {
|
|
compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
|
|
reg = <0 0x01c06000 0 0x2000>;
|
|
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_0_CLKREF_EN>,
|
|
<&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE_0_PIPE_CLK>;
|
|
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
|
|
|
|
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
|
|
reset-names = "phy";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1: pci@1c08000 {
|
|
compatible = "qcom,pcie-sm8350";
|
|
reg = <0 0x01c08000 0 0x3000>,
|
|
<0 0x40000000 0 0xf1d>,
|
|
<0 0x40000f20 0 0xa8>,
|
|
<0 0x40001000 0 0x1000>,
|
|
<0 0x40100000 0 0x100000>;
|
|
reg-names = "parf", "dbi", "elbi", "atu", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <1>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <2>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
|
|
|
|
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
|
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
|
|
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
|
|
clock-names = "aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave",
|
|
"slave_q2a",
|
|
"tbu",
|
|
"ddrss_sf_tbu",
|
|
"aggre1";
|
|
|
|
iommus = <&apps_smmu 0x1c80 0x7f>;
|
|
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
|
|
<0x100 &apps_smmu 0x1c81 0x1>;
|
|
|
|
resets = <&gcc GCC_PCIE_1_BCR>;
|
|
reset-names = "pci";
|
|
|
|
power-domains = <&gcc PCIE_1_GDSC>;
|
|
|
|
phys = <&pcie1_phy>;
|
|
phy-names = "pciephy";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1_phy: phy@1c0f000 {
|
|
compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
|
|
reg = <0 0x01c0e000 0 0x2000>;
|
|
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_1_CLKREF_EN>,
|
|
<&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE_1_PIPE_CLK>;
|
|
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
|
|
|
|
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
|
|
reset-names = "phy";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "pcie_1_pipe_clk";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ufs_mem_hc: ufshc@1d84000 {
|
|
compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
|
|
"jedec,ufs-2.0";
|
|
reg = <0 0x01d84000 0 0x3000>;
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufs_mem_phy_lanes>;
|
|
phy-names = "ufsphy";
|
|
lanes-per-direction = <2>;
|
|
#reset-cells = <1>;
|
|
resets = <&gcc GCC_UFS_PHY_BCR>;
|
|
reset-names = "rst";
|
|
|
|
power-domains = <&gcc UFS_PHY_GDSC>;
|
|
|
|
iommus = <&apps_smmu 0xe0 0x0>;
|
|
dma-coherent;
|
|
|
|
clock-names =
|
|
"core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
clocks =
|
|
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
|
freq-table-hz =
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ufs_mem_phy: phy@1d87000 {
|
|
compatible = "qcom,sm8350-qmp-ufs-phy";
|
|
reg = <0 0x01d87000 0 0x1c4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
clock-names = "ref",
|
|
"ref_aux";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
|
|
|
resets = <&ufs_mem_hc 0>;
|
|
reset-names = "ufsphy";
|
|
status = "disabled";
|
|
|
|
ufs_mem_phy_lanes: phy@1d87400 {
|
|
reg = <0 0x01d87400 0 0x188>,
|
|
<0 0x01d87600 0 0x200>,
|
|
<0 0x01d87c00 0 0x200>,
|
|
<0 0x01d87800 0 0x188>,
|
|
<0 0x01d87a00 0 0x200>;
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
|
|
ipa: ipa@1e40000 {
|
|
compatible = "qcom,sm8350-ipa";
|
|
|
|
iommus = <&apps_smmu 0x5c0 0x0>,
|
|
<&apps_smmu 0x5c2 0x0>;
|
|
reg = <0 0x01e40000 0 0x8000>,
|
|
<0 0x01e50000 0 0x4b20>,
|
|
<0 0x01e04000 0 0x23000>;
|
|
reg-names = "ipa-reg",
|
|
"ipa-shared",
|
|
"gsi";
|
|
|
|
interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
|
|
<&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "ipa",
|
|
"gsi",
|
|
"ipa-clock-query",
|
|
"ipa-setup-ready";
|
|
|
|
clocks = <&rpmhcc RPMH_IPA_CLK>;
|
|
clock-names = "core";
|
|
|
|
interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
|
|
interconnect-names = "memory",
|
|
"config";
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&ipa_smp2p_out 0>,
|
|
<&ipa_smp2p_out 1>;
|
|
qcom,smem-state-names = "ipa-clock-enabled-valid",
|
|
"ipa-clock-enabled";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
tcsr_mutex: hwlock@1f40000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
reg = <0x0 0x01f40000 0x0 0x40000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
gpu: gpu@3d00000 {
|
|
compatible = "qcom,adreno-660.1", "qcom,adreno";
|
|
|
|
reg = <0 0x03d00000 0 0x40000>,
|
|
<0 0x03d9e000 0 0x1000>,
|
|
<0 0x03d61000 0 0x800>;
|
|
reg-names = "kgsl_3d0_reg_memory",
|
|
"cx_mem",
|
|
"cx_dbgc";
|
|
|
|
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
|
|
|
|
operating-points-v2 = <&gpu_opp_table>;
|
|
|
|
qcom,gmu = <&gmu>;
|
|
|
|
status = "disabled";
|
|
|
|
zap-shader {
|
|
memory-region = <&pil_gpu_mem>;
|
|
};
|
|
|
|
/* note: downstream checks gpu binning for 670 Mhz */
|
|
gpu_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-840000000 {
|
|
opp-hz = /bits/ 64 <840000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
|
|
opp-778000000 {
|
|
opp-hz = /bits/ 64 <778000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
opp-738000000 {
|
|
opp-hz = /bits/ 64 <738000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
opp-676000000 {
|
|
opp-hz = /bits/ 64 <676000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
opp-608000000 {
|
|
opp-hz = /bits/ 64 <608000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
|
};
|
|
|
|
opp-540000000 {
|
|
opp-hz = /bits/ 64 <540000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
opp-491000000 {
|
|
opp-hz = /bits/ 64 <491000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
|
};
|
|
|
|
opp-443000000 {
|
|
opp-hz = /bits/ 64 <443000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
opp-379000000 {
|
|
opp-hz = /bits/ 64 <379000000>;
|
|
opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
|
|
};
|
|
|
|
opp-315000000 {
|
|
opp-hz = /bits/ 64 <315000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gmu: gmu@3d6a000 {
|
|
compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
|
|
|
|
reg = <0 0x03d6a000 0 0x34000>,
|
|
<0 0x03de0000 0 0x10000>,
|
|
<0 0x0b290000 0 0x10000>;
|
|
reg-names = "gmu", "rscc", "gmu_pdc";
|
|
|
|
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hfi", "gmu";
|
|
|
|
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
|
<&gpucc GPU_CC_CXO_CLK>,
|
|
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
|
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
|
<&gpucc GPU_CC_AHB_CLK>,
|
|
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
|
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
|
|
clock-names = "gmu",
|
|
"cxo",
|
|
"axi",
|
|
"memnoc",
|
|
"ahb",
|
|
"hub",
|
|
"smmu_vote";
|
|
|
|
power-domains = <&gpucc GPU_CX_GDSC>,
|
|
<&gpucc GPU_GX_GDSC>;
|
|
power-domain-names = "cx",
|
|
"gx";
|
|
|
|
iommus = <&adreno_smmu 5 0x400>;
|
|
|
|
operating-points-v2 = <&gmu_opp_table>;
|
|
|
|
gmu_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-200000000 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,sm8350-gpucc";
|
|
reg = <0 0x03d90000 0 0x9000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
|
clock-names = "bi_tcxo",
|
|
"gcc_gpu_gpll0_clk_src",
|
|
"gcc_gpu_gpll0_div_clk_src";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
adreno_smmu: iommu@3da0000 {
|
|
compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
|
|
reg = <0 0x03da0000 0 0x20000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <2>;
|
|
interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
|
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
|
<&gpucc GPU_CC_AHB_CLK>,
|
|
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
|
<&gpucc GPU_CC_CX_GMU_CLK>,
|
|
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
|
<&gpucc GPU_CC_HUB_AON_CLK>;
|
|
clock-names = "bus",
|
|
"iface",
|
|
"ahb",
|
|
"hlos1_vote_gpu_smmu",
|
|
"cx_gmu",
|
|
"hub_cx_int",
|
|
"hub_aon";
|
|
|
|
power-domains = <&gpucc GPU_CX_GDSC>;
|
|
dma-coherent;
|
|
};
|
|
|
|
lpass_ag_noc: interconnect@3c40000 {
|
|
compatible = "qcom,sm8350-lpass-ag-noc";
|
|
reg = <0 0x03c40000 0 0xf080>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mpss: remoteproc@4080000 {
|
|
compatible = "qcom,sm8350-mpss-pas";
|
|
reg = <0x0 0x04080000 0x0 0x4040>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready", "handover",
|
|
"stop-ack", "shutdown-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmhpd SM8350_CX>,
|
|
<&rpmhpd SM8350_MSS>;
|
|
power-domain-names = "cx", "mss";
|
|
|
|
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
|
|
|
|
memory-region = <&pil_modem_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_modem_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
label = "modem";
|
|
qcom,remote-pid = <1>;
|
|
};
|
|
};
|
|
|
|
slpi: remoteproc@5c00000 {
|
|
compatible = "qcom,sm8350-slpi-pas";
|
|
reg = <0 0x05c00000 0 0x4000>;
|
|
|
|
interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmhpd SM8350_LCX>,
|
|
<&rpmhpd SM8350_LMX>;
|
|
power-domain-names = "lcx", "lmx";
|
|
|
|
memory-region = <&pil_slpi_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_slpi_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_SLPI
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
label = "slpi";
|
|
qcom,remote-pid = <3>;
|
|
|
|
fastrpc {
|
|
compatible = "qcom,fastrpc";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
label = "sdsp";
|
|
qcom,non-secure-domain;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
compute-cb@1 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <1>;
|
|
iommus = <&apps_smmu 0x0541 0x0>;
|
|
};
|
|
|
|
compute-cb@2 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <2>;
|
|
iommus = <&apps_smmu 0x0542 0x0>;
|
|
};
|
|
|
|
compute-cb@3 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <3>;
|
|
iommus = <&apps_smmu 0x0543 0x0>;
|
|
/* note: shared-cb = <4> in downstream */
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
sdhc_2: mmc@8804000 {
|
|
compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
|
|
reg = <0 0x08804000 0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "iface", "core", "xo";
|
|
resets = <&gcc GCC_SDCC2_BCR>;
|
|
interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
|
|
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
|
iommus = <&apps_smmu 0x4a0 0x0>;
|
|
power-domains = <&rpmhpd SM8350_CX>;
|
|
operating-points-v2 = <&sdhc2_opp_table>;
|
|
bus-width = <4>;
|
|
dma-coherent;
|
|
|
|
status = "disabled";
|
|
|
|
sdhc2_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-202000000 {
|
|
opp-hz = /bits/ 64 <202000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
usb_1_hsphy: phy@88e3000 {
|
|
compatible = "qcom,sm8350-usb-hs-phy",
|
|
"qcom,usb-snps-hs-7nm-phy";
|
|
reg = <0 0x088e3000 0 0x400>;
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "ref";
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
|
};
|
|
|
|
usb_2_hsphy: phy@88e4000 {
|
|
compatible = "qcom,sm8250-usb-hs-phy",
|
|
"qcom,usb-snps-hs-7nm-phy";
|
|
reg = <0 0x088e4000 0 0x400>;
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "ref";
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
|
};
|
|
|
|
usb_1_qmpphy: phy-wrapper@88e9000 {
|
|
compatible = "qcom,sm8350-qmp-usb3-phy";
|
|
reg = <0 0x088e9000 0 0x200>,
|
|
<0 0x088e8000 0 0x20>;
|
|
status = "disabled";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
|
|
clock-names = "aux", "ref_clk_src", "com_aux";
|
|
|
|
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
|
|
<&gcc GCC_USB3_PHY_PRIM_BCR>;
|
|
reset-names = "phy", "common";
|
|
|
|
usb_1_ssphy: phy@88e9200 {
|
|
reg = <0 0x088e9200 0 0x200>,
|
|
<0 0x088e9400 0 0x200>,
|
|
<0 0x088e9c00 0 0x400>,
|
|
<0 0x088e9600 0 0x200>,
|
|
<0 0x088e9800 0 0x200>,
|
|
<0 0x088e9a00 0 0x100>;
|
|
#phy-cells = <0>;
|
|
#clock-cells = <0>;
|
|
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
|
clock-names = "pipe0";
|
|
clock-output-names = "usb3_phy_pipe_clk_src";
|
|
};
|
|
};
|
|
|
|
usb_2_qmpphy: phy-wrapper@88eb000 {
|
|
compatible = "qcom,sm8350-qmp-usb3-uni-phy";
|
|
reg = <0 0x088eb000 0 0x200>;
|
|
status = "disabled";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_USB3_SEC_CLKREF_EN>,
|
|
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
|
|
clock-names = "aux", "ref_clk_src", "ref", "com_aux";
|
|
|
|
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
|
|
<&gcc GCC_USB3_PHY_SEC_BCR>;
|
|
reset-names = "phy", "common";
|
|
|
|
usb_2_ssphy: phy@88ebe00 {
|
|
reg = <0 0x088ebe00 0 0x200>,
|
|
<0 0x088ec000 0 0x200>,
|
|
<0 0x088eb200 0 0x1100>;
|
|
#phy-cells = <0>;
|
|
#clock-cells = <0>;
|
|
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
|
|
clock-names = "pipe0";
|
|
clock-output-names = "usb3_uni_phy_pipe_clk_src";
|
|
};
|
|
};
|
|
|
|
dc_noc: interconnect@90c0000 {
|
|
compatible = "qcom,sm8350-dc-noc";
|
|
reg = <0 0x090c0000 0 0x4200>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
gem_noc: interconnect@9100000 {
|
|
compatible = "qcom,sm8350-gem-noc";
|
|
reg = <0 0x09100000 0 0xb4000>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
system-cache-controller@9200000 {
|
|
compatible = "qcom,sm8350-llcc";
|
|
reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
|
|
reg-names = "llcc_base", "llcc_broadcast_base";
|
|
};
|
|
|
|
compute_noc: interconnect@a0c0000 {
|
|
compatible = "qcom,sm8350-compute-noc";
|
|
reg = <0 0x0a0c0000 0 0xa180>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
usb_1: usb@a6f8800 {
|
|
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
|
|
reg = <0 0x0a6f8800 0 0x400>;
|
|
status = "disabled";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc",
|
|
"core",
|
|
"iface",
|
|
"sleep",
|
|
"mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <200000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 14 IRQ_TYPE_EDGE_BOTH>;
|
|
interrupt-names = "hs_phy_irq",
|
|
"ss_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"dp_hs_phy_irq";
|
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>;
|
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
|
|
|
usb_1_dwc3: usb@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x0a600000 0 0xcd00>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x0 0x0>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
};
|
|
};
|
|
|
|
usb_2: usb@a8f8800 {
|
|
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
|
|
reg = <0 0x0a8f8800 0 0x400>;
|
|
status = "disabled";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_USB30_SEC_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB3_SEC_CLKREF_EN>;
|
|
clock-names = "cfg_noc",
|
|
"core",
|
|
"iface",
|
|
"sleep",
|
|
"mock_utmi",
|
|
"xo";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_SEC_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <200000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 12 IRQ_TYPE_EDGE_BOTH>;
|
|
interrupt-names = "hs_phy_irq",
|
|
"ss_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"dp_hs_phy_irq";
|
|
|
|
power-domains = <&gcc USB30_SEC_GDSC>;
|
|
|
|
resets = <&gcc GCC_USB30_SEC_BCR>;
|
|
|
|
usb_2_dwc3: usb@a800000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x0a800000 0 0xcd00>;
|
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x20 0x0>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
};
|
|
};
|
|
|
|
mdss: display-subsystem@ae00000 {
|
|
compatible = "qcom,sm8350-mdss";
|
|
reg = <0 0x0ae00000 0 0x1000>;
|
|
reg-names = "mdss";
|
|
|
|
interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
|
|
interconnect-names = "mdp0-mem", "mdp1-mem";
|
|
|
|
power-domains = <&dispcc MDSS_GDSC>;
|
|
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&gcc GCC_DISP_SF_AXI_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
|
clock-names = "iface", "bus", "nrt_bus", "core";
|
|
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
iommus = <&apps_smmu 0x820 0x402>;
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
dpu_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
/* TODO: opp-200000000 should work with
|
|
* &rpmhpd_opp_low_svs, but one some of
|
|
* sm8350_hdk boards reboot using this
|
|
* opp.
|
|
*/
|
|
opp-200000000 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-345000000 {
|
|
opp-hz = /bits/ 64 <345000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-460000000 {
|
|
opp-hz = /bits/ 64 <460000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
};
|
|
};
|
|
|
|
mdss_mdp: display-controller@ae01000 {
|
|
compatible = "qcom,sm8350-dpu";
|
|
reg = <0 0x0ae01000 0 0x8f000>,
|
|
<0 0x0aeb0000 0 0x2008>;
|
|
reg-names = "mdp", "vbif";
|
|
|
|
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&gcc GCC_DISP_SF_AXI_CLK>,
|
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
|
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
|
clock-names = "bus",
|
|
"nrt_bus",
|
|
"iface",
|
|
"lut",
|
|
"core",
|
|
"vsync";
|
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
|
assigned-clock-rates = <19200000>;
|
|
|
|
operating-points-v2 = <&dpu_opp_table>;
|
|
power-domains = <&rpmhpd SM8350_MMCX>;
|
|
|
|
interrupt-parent = <&mdss>;
|
|
interrupts = <0>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
dpu_intf1_out: endpoint {
|
|
remote-endpoint = <&mdss_dsi0_in>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
dpu_intf2_out: endpoint {
|
|
remote-endpoint = <&mdss_dsi1_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi0: dsi@ae94000 {
|
|
compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
|
reg = <0 0x0ae94000 0 0x400>;
|
|
reg-names = "dsi_ctrl";
|
|
|
|
interrupt-parent = <&mdss>;
|
|
interrupts = <4>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>;
|
|
clock-names = "byte",
|
|
"byte_intf",
|
|
"pixel",
|
|
"core",
|
|
"iface",
|
|
"bus";
|
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
|
assigned-clock-parents = <&mdss_dsi0_phy 0>,
|
|
<&mdss_dsi0_phy 1>;
|
|
|
|
operating-points-v2 = <&dsi0_opp_table>;
|
|
power-domains = <&rpmhpd SM8350_MMCX>;
|
|
|
|
phys = <&mdss_dsi0_phy>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
dsi0_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
/* TODO: opp-187500000 should work with
|
|
* &rpmhpd_opp_low_svs, but one some of
|
|
* sm8350_hdk boards reboot using this
|
|
* opp.
|
|
*/
|
|
opp-187500000 {
|
|
opp-hz = /bits/ 64 <187500000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-358000000 {
|
|
opp-hz = /bits/ 64 <358000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
mdss_dsi0_in: endpoint {
|
|
remote-endpoint = <&dpu_intf1_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
mdss_dsi0_out: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi0_phy: phy@ae94400 {
|
|
compatible = "qcom,sm8350-dsi-phy-5nm";
|
|
reg = <0 0x0ae94400 0 0x200>,
|
|
<0 0x0ae94600 0 0x280>,
|
|
<0 0x0ae94900 0 0x27c>;
|
|
reg-names = "dsi_phy",
|
|
"dsi_phy_lane",
|
|
"dsi_pll";
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "iface", "ref";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdss_dsi1: dsi@ae96000 {
|
|
compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
|
reg = <0 0x0ae96000 0 0x400>;
|
|
reg-names = "dsi_ctrl";
|
|
|
|
interrupt-parent = <&mdss>;
|
|
interrupts = <5>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>;
|
|
clock-names = "byte",
|
|
"byte_intf",
|
|
"pixel",
|
|
"core",
|
|
"iface",
|
|
"bus";
|
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
|
assigned-clock-parents = <&mdss_dsi1_phy 0>,
|
|
<&mdss_dsi1_phy 1>;
|
|
|
|
operating-points-v2 = <&dsi1_opp_table>;
|
|
power-domains = <&rpmhpd SM8350_MMCX>;
|
|
|
|
phys = <&mdss_dsi1_phy>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
dsi1_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
/* TODO: opp-187500000 should work with
|
|
* &rpmhpd_opp_low_svs, but one some of
|
|
* sm8350_hdk boards reboot using this
|
|
* opp.
|
|
*/
|
|
opp-187500000 {
|
|
opp-hz = /bits/ 64 <187500000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-358000000 {
|
|
opp-hz = /bits/ 64 <358000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
mdss_dsi1_in: endpoint {
|
|
remote-endpoint = <&dpu_intf2_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
mdss_dsi1_out: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi1_phy: phy@ae96400 {
|
|
compatible = "qcom,sm8350-dsi-phy-5nm";
|
|
reg = <0 0x0ae96400 0 0x200>,
|
|
<0 0x0ae96600 0 0x280>,
|
|
<0 0x0ae96900 0 0x27c>;
|
|
reg-names = "dsi_phy",
|
|
"dsi_phy_lane",
|
|
"dsi_pll";
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "iface", "ref";
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,sm8350-dispcc";
|
|
reg = <0 0x0af00000 0 0x10000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
|
|
<&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
|
|
<0>,
|
|
<0>;
|
|
clock-names = "bi_tcxo",
|
|
"dsi0_phy_pll_out_byteclk",
|
|
"dsi0_phy_pll_out_dsiclk",
|
|
"dsi1_phy_pll_out_byteclk",
|
|
"dsi1_phy_pll_out_dsiclk",
|
|
"dp_phy_pll_link_clk",
|
|
"dp_phy_pll_vco_div_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
|
|
power-domains = <&rpmhpd SM8350_MMCX>;
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sm8350-pdc", "qcom,pdc";
|
|
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
|
|
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
|
|
<59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
|
|
<69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
|
|
<156 716 12>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
tsens0: thermal-sensor@c263000 {
|
|
compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
|
|
reg = <0 0x0c263000 0 0x1ff>, /* TM */
|
|
<0 0x0c222000 0 0x8>; /* SROT */
|
|
#qcom,sensors = <15>;
|
|
interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens1: thermal-sensor@c265000 {
|
|
compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
|
|
reg = <0 0x0c265000 0 0x1ff>, /* TM */
|
|
<0 0x0c223000 0 0x8>; /* SROT */
|
|
#qcom,sensors = <14>;
|
|
interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
aoss_qmp: power-management@c300000 {
|
|
compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
|
|
reg = <0 0x0c300000 0 0x400>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sram@c3f0000 {
|
|
compatible = "qcom,rpmh-stats";
|
|
reg = <0 0x0c3f0000 0 0x400>;
|
|
};
|
|
|
|
spmi_bus: spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x0 0x0c440000 0x0 0x1100>,
|
|
<0x0 0x0c600000 0x0 0x2000000>,
|
|
<0x0 0x0e600000 0x0 0x100000>,
|
|
<0x0 0x0e700000 0x0 0xa0000>,
|
|
<0x0 0x0c40a000 0x0 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
};
|
|
|
|
tlmm: pinctrl@f100000 {
|
|
compatible = "qcom,sm8350-tlmm";
|
|
reg = <0 0x0f100000 0 0x300000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&tlmm 0 0 204>;
|
|
wakeup-parent = <&pdc>;
|
|
|
|
sdc2_default_state: sdc2-default-state {
|
|
clk-pins {
|
|
pins = "sdc2_clk";
|
|
drive-strength = <16>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "sdc2_cmd";
|
|
drive-strength = <16>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "sdc2_data";
|
|
drive-strength = <16>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdc2_sleep_state: sdc2-sleep-state {
|
|
clk-pins {
|
|
pins = "sdc2_clk";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "sdc2_cmd";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "sdc2_data";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qup_uart3_default_state: qup-uart3-default-state {
|
|
rx-pins {
|
|
pins = "gpio18";
|
|
function = "qup3";
|
|
};
|
|
tx-pins {
|
|
pins = "gpio19";
|
|
function = "qup3";
|
|
};
|
|
};
|
|
|
|
qup_uart6_default: qup-uart6-default-state {
|
|
pins = "gpio30", "gpio31";
|
|
function = "qup6";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_uart18_default: qup-uart18-default-state {
|
|
pins = "gpio58", "gpio59";
|
|
function = "qup18";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c0_default: qup-i2c0-default-state {
|
|
pins = "gpio4", "gpio5";
|
|
function = "qup0";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c1_default: qup-i2c1-default-state {
|
|
pins = "gpio8", "gpio9";
|
|
function = "qup1";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c2_default: qup-i2c2-default-state {
|
|
pins = "gpio12", "gpio13";
|
|
function = "qup2";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c4_default: qup-i2c4-default-state {
|
|
pins = "gpio20", "gpio21";
|
|
function = "qup4";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c5_default: qup-i2c5-default-state {
|
|
pins = "gpio24", "gpio25";
|
|
function = "qup5";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c6_default: qup-i2c6-default-state {
|
|
pins = "gpio28", "gpio29";
|
|
function = "qup6";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c7_default: qup-i2c7-default-state {
|
|
pins = "gpio32", "gpio33";
|
|
function = "qup7";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c8_default: qup-i2c8-default-state {
|
|
pins = "gpio36", "gpio37";
|
|
function = "qup8";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c9_default: qup-i2c9-default-state {
|
|
pins = "gpio40", "gpio41";
|
|
function = "qup9";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c10_default: qup-i2c10-default-state {
|
|
pins = "gpio44", "gpio45";
|
|
function = "qup10";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c11_default: qup-i2c11-default-state {
|
|
pins = "gpio48", "gpio49";
|
|
function = "qup11";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c12_default: qup-i2c12-default-state {
|
|
pins = "gpio52", "gpio53";
|
|
function = "qup12";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c13_default: qup-i2c13-default-state {
|
|
pins = "gpio0", "gpio1";
|
|
function = "qup13";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c14_default: qup-i2c14-default-state {
|
|
pins = "gpio56", "gpio57";
|
|
function = "qup14";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c15_default: qup-i2c15-default-state {
|
|
pins = "gpio60", "gpio61";
|
|
function = "qup15";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c16_default: qup-i2c16-default-state {
|
|
pins = "gpio64", "gpio65";
|
|
function = "qup16";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c17_default: qup-i2c17-default-state {
|
|
pins = "gpio72", "gpio73";
|
|
function = "qup17";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c19_default: qup-i2c19-default-state {
|
|
pins = "gpio76", "gpio77";
|
|
function = "qup19";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
apps_smmu: iommu@15000000 {
|
|
compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
|
|
reg = <0 0x15000000 0 0x100000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <2>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
adsp: remoteproc@17300000 {
|
|
compatible = "qcom,sm8350-adsp-pas";
|
|
reg = <0 0x17300000 0 0x100>;
|
|
|
|
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmhpd SM8350_LCX>,
|
|
<&rpmhpd SM8350_LMX>;
|
|
power-domain-names = "lcx", "lmx";
|
|
|
|
memory-region = <&pil_adsp_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_adsp_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
label = "lpass";
|
|
qcom,remote-pid = <2>;
|
|
|
|
fastrpc {
|
|
compatible = "qcom,fastrpc";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
label = "adsp";
|
|
qcom,non-secure-domain;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
compute-cb@3 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <3>;
|
|
iommus = <&apps_smmu 0x1803 0x0>;
|
|
};
|
|
|
|
compute-cb@4 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <4>;
|
|
iommus = <&apps_smmu 0x1804 0x0>;
|
|
};
|
|
|
|
compute-cb@5 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <5>;
|
|
iommus = <&apps_smmu 0x1805 0x0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0 0x20000>;
|
|
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
|
|
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
timer@17c20000 {
|
|
compatible = "arm,armv7-timer-mem";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0x20000000>;
|
|
reg = <0x0 0x17c20000 0x0 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@17c21000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c21000 0x1000>,
|
|
<0x17c22000 0x1000>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c23000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c25000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c27000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c29000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c2b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c2d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x0 0x18200000 0x0 0x10000>,
|
|
<0x0 0x18210000 0x0 0x10000>,
|
|
<0x0 0x18220000 0x0 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>, <CONTROL_TCS 0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sm8350-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
clock-names = "xo";
|
|
clocks = <&xo_board>;
|
|
};
|
|
|
|
rpmhpd: power-controller {
|
|
compatible = "qcom,sm8350-rpmhpd";
|
|
#power-domain-cells = <1>;
|
|
operating-points-v2 = <&rpmhpd_opp_table>;
|
|
|
|
rpmhpd_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
rpmhpd_opp_ret: opp1 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
};
|
|
|
|
rpmhpd_opp_min_svs: opp2 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs: opp3 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs: opp4 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l1: opp5 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom: opp6 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l1: opp7 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l2: opp8 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo: opp9 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l1: opp10 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
apps_bcm_voter: bcm-voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@18591000 {
|
|
compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
|
|
reg = <0 0x18591000 0 0x1000>,
|
|
<0 0x18592000 0 0x1000>,
|
|
<0 0x18593000 0 0x1000>;
|
|
reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
|
|
#freq-domain-cells = <1>;
|
|
};
|
|
|
|
cdsp: remoteproc@98900000 {
|
|
compatible = "qcom,sm8350-cdsp-pas";
|
|
reg = <0 0x98900000 0 0x1400000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmhpd SM8350_CX>,
|
|
<&rpmhpd SM8350_MXC>;
|
|
power-domain-names = "cx", "mxc";
|
|
|
|
interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
|
|
|
|
memory-region = <&pil_cdsp_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_cdsp_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
label = "cdsp";
|
|
qcom,remote-pid = <5>;
|
|
|
|
fastrpc {
|
|
compatible = "qcom,fastrpc";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
label = "cdsp";
|
|
qcom,non-secure-domain;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
compute-cb@1 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <1>;
|
|
iommus = <&apps_smmu 0x2161 0x0400>,
|
|
<&apps_smmu 0x1181 0x0420>;
|
|
};
|
|
|
|
compute-cb@2 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <2>;
|
|
iommus = <&apps_smmu 0x2162 0x0400>,
|
|
<&apps_smmu 0x1182 0x0420>;
|
|
};
|
|
|
|
compute-cb@3 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <3>;
|
|
iommus = <&apps_smmu 0x2163 0x0400>,
|
|
<&apps_smmu 0x1183 0x0420>;
|
|
};
|
|
|
|
compute-cb@4 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <4>;
|
|
iommus = <&apps_smmu 0x2164 0x0400>,
|
|
<&apps_smmu 0x1184 0x0420>;
|
|
};
|
|
|
|
compute-cb@5 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <5>;
|
|
iommus = <&apps_smmu 0x2165 0x0400>,
|
|
<&apps_smmu 0x1185 0x0420>;
|
|
};
|
|
|
|
compute-cb@6 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <6>;
|
|
iommus = <&apps_smmu 0x2166 0x0400>,
|
|
<&apps_smmu 0x1186 0x0420>;
|
|
};
|
|
|
|
compute-cb@7 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <7>;
|
|
iommus = <&apps_smmu 0x2167 0x0400>,
|
|
<&apps_smmu 0x1187 0x0420>;
|
|
};
|
|
|
|
compute-cb@8 {
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
reg = <8>;
|
|
iommus = <&apps_smmu 0x2168 0x0400>,
|
|
<&apps_smmu 0x1188 0x0420>;
|
|
};
|
|
|
|
/* note: secure cb9 in downstream */
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
cpu0-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 1>;
|
|
|
|
trips {
|
|
cpu0_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu0_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu0_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu0_alert0>;
|
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu0_alert1>;
|
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu1-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 2>;
|
|
|
|
trips {
|
|
cpu1_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu1_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu1_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu1_alert0>;
|
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu1_alert1>;
|
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu2-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 3>;
|
|
|
|
trips {
|
|
cpu2_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu2_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu2_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu2_alert0>;
|
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu2_alert1>;
|
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu3-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 4>;
|
|
|
|
trips {
|
|
cpu3_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu3_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu3_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu3_alert0>;
|
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu3_alert1>;
|
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu4-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 7>;
|
|
|
|
trips {
|
|
cpu4_top_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu4_top_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu4_top_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu4_top_alert0>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu4_top_alert1>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu5-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 8>;
|
|
|
|
trips {
|
|
cpu5_top_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu5_top_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu5_top_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu5_top_alert0>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu5_top_alert1>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu6-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 9>;
|
|
|
|
trips {
|
|
cpu6_top_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu6_top_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu6_top_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu6_top_alert0>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu6_top_alert1>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu7-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 10>;
|
|
|
|
trips {
|
|
cpu7_top_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu7_top_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu7_top_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu7_top_alert0>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu7_top_alert1>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu4-bottom-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 11>;
|
|
|
|
trips {
|
|
cpu4_bottom_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu4_bottom_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu4_bottom_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu4_bottom_alert0>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu4_bottom_alert1>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu5-bottom-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 12>;
|
|
|
|
trips {
|
|
cpu5_bottom_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu5_bottom_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu5_bottom_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu5_bottom_alert0>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu5_bottom_alert1>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu6-bottom-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 13>;
|
|
|
|
trips {
|
|
cpu6_bottom_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu6_bottom_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu6_bottom_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu6_bottom_alert0>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu6_bottom_alert1>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu7-bottom-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 14>;
|
|
|
|
trips {
|
|
cpu7_bottom_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu7_bottom_alert1: trip-point1 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu7_bottom_crit: cpu-crit {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu7_bottom_alert0>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu7_bottom_alert1>;
|
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss0-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 0>;
|
|
|
|
trips {
|
|
aoss0_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
cluster0-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 5>;
|
|
|
|
trips {
|
|
cluster0_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
cluster0_crit: cluster0_crit {
|
|
temperature = <110000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cluster1-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 6>;
|
|
|
|
trips {
|
|
cluster1_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
cluster1_crit: cluster1_crit {
|
|
temperature = <110000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss1-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 0>;
|
|
|
|
trips {
|
|
aoss1_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 1>;
|
|
|
|
trips {
|
|
gpu1_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu-bottom-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 2>;
|
|
|
|
trips {
|
|
gpu2_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
nspss1-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 3>;
|
|
|
|
trips {
|
|
nspss1_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
nspss2-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 4>;
|
|
|
|
trips {
|
|
nspss2_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
nspss3-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 5>;
|
|
|
|
trips {
|
|
nspss3_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
video-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 6>;
|
|
|
|
trips {
|
|
video_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
mem-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 7>;
|
|
|
|
trips {
|
|
mem_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem1-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 8>;
|
|
|
|
trips {
|
|
modem1_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem2-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 9>;
|
|
|
|
trips {
|
|
modem2_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem3-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 10>;
|
|
|
|
trips {
|
|
modem3_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem4-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 11>;
|
|
|
|
trips {
|
|
modem4_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
camera-top-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 12>;
|
|
|
|
trips {
|
|
camera1_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
cam-bottom-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 13>;
|
|
|
|
trips {
|
|
camera2_alert0: trip-point0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|