373 lines
13 KiB
C
373 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ASM_ESR_H
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#define __ASM_ESR_H
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#include <asm/memory.h>
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#include <asm/sysreg.h>
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#define ESR_ELx_EC_UNKNOWN (0x00)
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#define ESR_ELx_EC_WFx (0x01)
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/* Unallocated EC: 0x02 */
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#define ESR_ELx_EC_CP15_32 (0x03)
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#define ESR_ELx_EC_CP15_64 (0x04)
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#define ESR_ELx_EC_CP14_MR (0x05)
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#define ESR_ELx_EC_CP14_LS (0x06)
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#define ESR_ELx_EC_FP_ASIMD (0x07)
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#define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
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#define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
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/* Unallocated EC: 0x0A - 0x0B */
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#define ESR_ELx_EC_CP14_64 (0x0C)
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#define ESR_ELx_EC_BTI (0x0D)
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#define ESR_ELx_EC_ILL (0x0E)
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/* Unallocated EC: 0x0F - 0x10 */
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#define ESR_ELx_EC_SVC32 (0x11)
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#define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
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#define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
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/* Unallocated EC: 0x14 */
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#define ESR_ELx_EC_SVC64 (0x15)
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#define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
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#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
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#define ESR_ELx_EC_SYS64 (0x18)
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#define ESR_ELx_EC_SVE (0x19)
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#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
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/* Unallocated EC: 0x1B */
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#define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */
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#define ESR_ELx_EC_SME (0x1D)
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/* Unallocated EC: 0x1E */
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#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
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#define ESR_ELx_EC_IABT_LOW (0x20)
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#define ESR_ELx_EC_IABT_CUR (0x21)
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#define ESR_ELx_EC_PC_ALIGN (0x22)
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/* Unallocated EC: 0x23 */
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#define ESR_ELx_EC_DABT_LOW (0x24)
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#define ESR_ELx_EC_DABT_CUR (0x25)
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#define ESR_ELx_EC_SP_ALIGN (0x26)
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/* Unallocated EC: 0x27 */
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#define ESR_ELx_EC_FP_EXC32 (0x28)
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/* Unallocated EC: 0x29 - 0x2B */
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#define ESR_ELx_EC_FP_EXC64 (0x2C)
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/* Unallocated EC: 0x2D - 0x2E */
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#define ESR_ELx_EC_SERROR (0x2F)
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#define ESR_ELx_EC_BREAKPT_LOW (0x30)
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#define ESR_ELx_EC_BREAKPT_CUR (0x31)
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#define ESR_ELx_EC_SOFTSTP_LOW (0x32)
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#define ESR_ELx_EC_SOFTSTP_CUR (0x33)
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#define ESR_ELx_EC_WATCHPT_LOW (0x34)
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#define ESR_ELx_EC_WATCHPT_CUR (0x35)
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/* Unallocated EC: 0x36 - 0x37 */
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#define ESR_ELx_EC_BKPT32 (0x38)
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/* Unallocated EC: 0x39 */
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#define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
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/* Unallocated EC: 0x3B */
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#define ESR_ELx_EC_BRK64 (0x3C)
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/* Unallocated EC: 0x3D - 0x3F */
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#define ESR_ELx_EC_MAX (0x3F)
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#define ESR_ELx_EC_SHIFT (26)
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#define ESR_ELx_EC_WIDTH (6)
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#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
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#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
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#define ESR_ELx_IL_SHIFT (25)
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#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
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#define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1)
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#define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK)
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/* ISS field definitions shared by different classes */
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#define ESR_ELx_WNR_SHIFT (6)
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#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
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/* Asynchronous Error Type */
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#define ESR_ELx_IDS_SHIFT (24)
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#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
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#define ESR_ELx_AET_SHIFT (10)
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#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
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/* Shared ISS field definitions for Data/Instruction aborts */
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#define ESR_ELx_SET_SHIFT (11)
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#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
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#define ESR_ELx_FnV_SHIFT (10)
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#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
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#define ESR_ELx_EA_SHIFT (9)
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#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
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#define ESR_ELx_S1PTW_SHIFT (7)
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#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
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/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
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#define ESR_ELx_FSC (0x3F)
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#define ESR_ELx_FSC_TYPE (0x3C)
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#define ESR_ELx_FSC_LEVEL (0x03)
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#define ESR_ELx_FSC_EXTABT (0x10)
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#define ESR_ELx_FSC_MTE (0x11)
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#define ESR_ELx_FSC_SERROR (0x11)
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#define ESR_ELx_FSC_ACCESS (0x08)
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#define ESR_ELx_FSC_FAULT (0x04)
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#define ESR_ELx_FSC_PERM (0x0C)
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#define ESR_ELx_FSC_SEA_TTW0 (0x14)
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#define ESR_ELx_FSC_SEA_TTW1 (0x15)
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#define ESR_ELx_FSC_SEA_TTW2 (0x16)
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#define ESR_ELx_FSC_SEA_TTW3 (0x17)
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#define ESR_ELx_FSC_SECC (0x18)
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#define ESR_ELx_FSC_SECC_TTW0 (0x1c)
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#define ESR_ELx_FSC_SECC_TTW1 (0x1d)
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#define ESR_ELx_FSC_SECC_TTW2 (0x1e)
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#define ESR_ELx_FSC_SECC_TTW3 (0x1f)
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/* ISS field definitions for Data Aborts */
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#define ESR_ELx_ISV_SHIFT (24)
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#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
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#define ESR_ELx_SAS_SHIFT (22)
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#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
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#define ESR_ELx_SSE_SHIFT (21)
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#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
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#define ESR_ELx_SRT_SHIFT (16)
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#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
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#define ESR_ELx_SF_SHIFT (15)
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#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
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#define ESR_ELx_AR_SHIFT (14)
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#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
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#define ESR_ELx_CM_SHIFT (8)
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#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
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/* ISS field definitions for exceptions taken in to Hyp */
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#define ESR_ELx_CV (UL(1) << 24)
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#define ESR_ELx_COND_SHIFT (20)
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#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
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#define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
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#define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
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#define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
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#define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
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#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
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#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
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#define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
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#define DISR_EL1_IDS (UL(1) << 24)
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/*
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* DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
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* different things in the future...
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*/
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#define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
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/* ESR value templates for specific events */
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#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \
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(ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))
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#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
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ESR_ELx_WFx_ISS_WFI)
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/* BRK instruction trap from AArch64 state */
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#define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff
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/* ISS field definitions for System instruction traps */
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#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
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#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
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#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
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#define ESR_ELx_SYS64_ISS_DIR_READ 0x1
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#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
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#define ESR_ELx_SYS64_ISS_RT_SHIFT 5
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#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
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#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
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#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
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#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
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#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
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#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
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#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
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#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
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#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
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ESR_ELx_SYS64_ISS_OP1_MASK | \
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ESR_ELx_SYS64_ISS_OP2_MASK | \
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ESR_ELx_SYS64_ISS_CRN_MASK | \
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ESR_ELx_SYS64_ISS_CRM_MASK)
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#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
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(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
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((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
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((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
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((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
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((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
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#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
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ESR_ELx_SYS64_ISS_DIR_MASK)
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#define ESR_ELx_SYS64_ISS_RT(esr) \
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(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
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/*
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* User space cache operations have the following sysreg encoding
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* in System instructions.
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* op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
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*/
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#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
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#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
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#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
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#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
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#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
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#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
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#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
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ESR_ELx_SYS64_ISS_OP1_MASK | \
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ESR_ELx_SYS64_ISS_OP2_MASK | \
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ESR_ELx_SYS64_ISS_CRN_MASK | \
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ESR_ELx_SYS64_ISS_DIR_MASK)
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#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
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(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
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ESR_ELx_SYS64_ISS_DIR_WRITE)
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/*
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* User space MRS operations which are supported for emulation
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* have the following sysreg encoding in System instructions.
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* op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
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*/
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#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
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ESR_ELx_SYS64_ISS_OP1_MASK | \
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ESR_ELx_SYS64_ISS_CRN_MASK | \
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ESR_ELx_SYS64_ISS_DIR_MASK)
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#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
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(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
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#define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define esr_sys64_to_sysreg(e) \
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sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
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ESR_ELx_SYS64_ISS_OP0_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
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ESR_ELx_SYS64_ISS_OP1_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
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ESR_ELx_SYS64_ISS_CRN_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
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ESR_ELx_SYS64_ISS_CRM_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
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ESR_ELx_SYS64_ISS_OP2_SHIFT))
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#define esr_cp15_to_sysreg(e) \
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sys_reg(3, \
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(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
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ESR_ELx_SYS64_ISS_OP1_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
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ESR_ELx_SYS64_ISS_CRN_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
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ESR_ELx_SYS64_ISS_CRM_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
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ESR_ELx_SYS64_ISS_OP2_SHIFT))
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/* ISS field definitions for ERET/ERETAA/ERETAB trapping */
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#define ESR_ELx_ERET_ISS_ERET 0x2
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#define ESR_ELx_ERET_ISS_ERETA 0x1
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/*
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* ISS field definitions for floating-point exception traps
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* (FP_EXC_32/FP_EXC_64).
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*
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* (The FPEXC_* constants are used instead for common bits.)
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*/
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#define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
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/*
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* ISS field definitions for CP15 accesses
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*/
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#define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
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#define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
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#define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
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#define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
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#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
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#define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
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#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
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#define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
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#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
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#define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
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#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
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#define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
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#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
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#define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \
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ESR_ELx_CP15_32_ISS_OP2_MASK | \
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ESR_ELx_CP15_32_ISS_CRN_MASK | \
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ESR_ELx_CP15_32_ISS_CRM_MASK | \
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ESR_ELx_CP15_32_ISS_DIR_MASK)
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#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
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(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
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((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
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((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
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((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
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#define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
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#define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
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#define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
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#define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
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#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
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#define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
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#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
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#define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
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#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
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#define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
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#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
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#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
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(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
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((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
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#define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \
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ESR_ELx_CP15_64_ISS_CRM_MASK | \
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ESR_ELx_CP15_64_ISS_DIR_MASK)
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#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
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ESR_ELx_CP15_64_ISS_DIR_READ)
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#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
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ESR_ELx_CP15_64_ISS_DIR_READ)
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#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
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ESR_ELx_CP15_32_ISS_DIR_READ)
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/*
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* ISS values for SME traps
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*/
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#define ESR_ELx_SME_ISS_SME_DISABLED 0
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#define ESR_ELx_SME_ISS_ILL 1
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#define ESR_ELx_SME_ISS_SM_DISABLED 2
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#define ESR_ELx_SME_ISS_ZA_DISABLED 3
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#define ESR_ELx_SME_ISS_ZT_DISABLED 4
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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static inline bool esr_is_data_abort(unsigned long esr)
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{
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const unsigned long ec = ESR_ELx_EC(esr);
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return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
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}
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const char *esr_get_class_string(unsigned long esr);
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#endif /* __ASSEMBLY */
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#endif /* __ASM_ESR_H */
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