351 lines
12 KiB
C
351 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015, 2016 ARM Ltd.
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*/
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#ifndef __KVM_ARM_VGIC_NEW_H__
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#define __KVM_ARM_VGIC_NEW_H__
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#include <linux/irqchip/arm-gic-common.h>
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#include <asm/kvm_mmu.h>
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#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
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#define IMPLEMENTER_ARM 0x43b
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#define VGIC_ADDR_UNDEF (-1)
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#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
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#define INTERRUPT_ID_BITS_SPIS 10
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#define INTERRUPT_ID_BITS_ITS 16
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#define VGIC_PRI_BITS 5
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#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
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#define VGIC_AFFINITY_0_SHIFT 0
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#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
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#define VGIC_AFFINITY_1_SHIFT 8
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#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
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#define VGIC_AFFINITY_2_SHIFT 16
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#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
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#define VGIC_AFFINITY_3_SHIFT 24
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#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
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#define VGIC_AFFINITY_LEVEL(reg, level) \
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((((reg) & VGIC_AFFINITY_## level ##_MASK) \
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>> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
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/*
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* The Userspace encodes the affinity differently from the MPIDR,
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* Below macro converts vgic userspace format to MPIDR reg format.
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*/
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#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
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VGIC_AFFINITY_LEVEL(val, 1) | \
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VGIC_AFFINITY_LEVEL(val, 2) | \
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VGIC_AFFINITY_LEVEL(val, 3))
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/*
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* As per Documentation/virt/kvm/devices/arm-vgic-v3.rst,
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* below macros are defined for CPUREG encoding.
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*/
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#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
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#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
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#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
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#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
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#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
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#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
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#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
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#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
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#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
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#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
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#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
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KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
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KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
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KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
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KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
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/*
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* As per Documentation/virt/kvm/devices/arm-vgic-its.rst,
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* below macros are defined for ITS table entry encoding.
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*/
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#define KVM_ITS_CTE_VALID_SHIFT 63
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#define KVM_ITS_CTE_VALID_MASK BIT_ULL(63)
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#define KVM_ITS_CTE_RDBASE_SHIFT 16
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#define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
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#define KVM_ITS_ITE_NEXT_SHIFT 48
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#define KVM_ITS_ITE_PINTID_SHIFT 16
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#define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
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#define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
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#define KVM_ITS_DTE_VALID_SHIFT 63
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#define KVM_ITS_DTE_VALID_MASK BIT_ULL(63)
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#define KVM_ITS_DTE_NEXT_SHIFT 49
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#define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
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#define KVM_ITS_DTE_ITTADDR_SHIFT 5
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#define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
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#define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
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#define KVM_ITS_L1E_VALID_MASK BIT_ULL(63)
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/* we only support 64 kB translation table page size */
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#define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
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#define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0)
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#define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12)
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#define KVM_VGIC_V3_RDIST_FLAGS_SHIFT 12
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#define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(51, 16)
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#define KVM_VGIC_V3_RDIST_COUNT_MASK GENMASK_ULL(63, 52)
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#define KVM_VGIC_V3_RDIST_COUNT_SHIFT 52
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#ifdef CONFIG_DEBUG_SPINLOCK
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#define DEBUG_SPINLOCK_BUG_ON(p) BUG_ON(p)
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#else
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#define DEBUG_SPINLOCK_BUG_ON(p)
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#endif
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static inline u32 vgic_get_implementation_rev(struct kvm_vcpu *vcpu)
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{
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return vcpu->kvm->arch.vgic.implementation_rev;
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}
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/* Requires the irq_lock to be held by the caller. */
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static inline bool irq_is_pending(struct vgic_irq *irq)
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{
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if (irq->config == VGIC_CONFIG_EDGE)
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return irq->pending_latch;
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else
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return irq->pending_latch || irq->line_level;
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}
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static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq)
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{
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return irq->config == VGIC_CONFIG_LEVEL && irq->hw;
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}
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static inline int vgic_irq_get_lr_count(struct vgic_irq *irq)
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{
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/* Account for the active state as an interrupt */
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if (vgic_irq_is_sgi(irq->intid) && irq->source)
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return hweight8(irq->source) + irq->active;
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return irq_is_pending(irq) || irq->active;
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}
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static inline bool vgic_irq_is_multi_sgi(struct vgic_irq *irq)
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{
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return vgic_irq_get_lr_count(irq) > 1;
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}
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static inline int vgic_write_guest_lock(struct kvm *kvm, gpa_t gpa,
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const void *data, unsigned long len)
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{
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struct vgic_dist *dist = &kvm->arch.vgic;
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int ret;
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dist->table_write_in_progress = true;
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ret = kvm_write_guest_lock(kvm, gpa, data, len);
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dist->table_write_in_progress = false;
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return ret;
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}
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/*
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* This struct provides an intermediate representation of the fields contained
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* in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
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* state to userspace can generate either GICv2 or GICv3 CPU interface
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* registers regardless of the hardware backed GIC used.
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*/
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struct vgic_vmcr {
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u32 grpen0;
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u32 grpen1;
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u32 ackctl;
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u32 fiqen;
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u32 cbpr;
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u32 eoim;
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u32 abpr;
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u32 bpr;
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u32 pmr; /* Priority mask field in the GICC_PMR and
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* ICC_PMR_EL1 priority field format */
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};
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struct vgic_reg_attr {
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struct kvm_vcpu *vcpu;
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gpa_t addr;
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};
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int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
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struct vgic_reg_attr *reg_attr);
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int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
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struct vgic_reg_attr *reg_attr);
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const struct vgic_register_region *
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vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
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gpa_t addr, int len);
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struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
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u32 intid);
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void __vgic_put_lpi_locked(struct kvm *kvm, struct vgic_irq *irq);
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void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
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bool vgic_get_phys_line_level(struct vgic_irq *irq);
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void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending);
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void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active);
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bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
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unsigned long flags);
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void vgic_kick_vcpus(struct kvm *kvm);
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void vgic_irq_handle_resampling(struct vgic_irq *irq,
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bool lr_deactivated, bool lr_pending);
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int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr,
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phys_addr_t addr, phys_addr_t alignment,
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phys_addr_t size);
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void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
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void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
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void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
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void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
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void vgic_v2_set_npie(struct kvm_vcpu *vcpu);
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int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
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int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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int offset, u32 *val);
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int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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int offset, u32 *val);
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void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void vgic_v2_enable(struct kvm_vcpu *vcpu);
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int vgic_v2_probe(const struct gic_kvm_info *info);
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int vgic_v2_map_resources(struct kvm *kvm);
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int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
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enum vgic_type);
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void vgic_v2_init_lrs(void);
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void vgic_v2_load(struct kvm_vcpu *vcpu);
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void vgic_v2_put(struct kvm_vcpu *vcpu);
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void vgic_v2_vmcr_sync(struct kvm_vcpu *vcpu);
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void vgic_v2_save_state(struct kvm_vcpu *vcpu);
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void vgic_v2_restore_state(struct kvm_vcpu *vcpu);
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static inline void vgic_get_irq_kref(struct vgic_irq *irq)
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{
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if (irq->intid < VGIC_MIN_LPI)
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return;
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kref_get(&irq->refcount);
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}
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void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
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void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
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void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
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void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
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void vgic_v3_set_npie(struct kvm_vcpu *vcpu);
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void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void vgic_v3_enable(struct kvm_vcpu *vcpu);
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int vgic_v3_probe(const struct gic_kvm_info *info);
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int vgic_v3_map_resources(struct kvm *kvm);
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int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
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int vgic_v3_save_pending_tables(struct kvm *kvm);
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int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count);
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int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
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bool vgic_v3_check_base(struct kvm *kvm);
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void vgic_v3_load(struct kvm_vcpu *vcpu);
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void vgic_v3_put(struct kvm_vcpu *vcpu);
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void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu);
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bool vgic_has_its(struct kvm *kvm);
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int kvm_vgic_register_its_device(void);
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void vgic_enable_lpis(struct kvm_vcpu *vcpu);
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void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu);
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int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
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int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
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int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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int offset, u32 *val);
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int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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int offset, u32 *val);
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int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr, bool is_write);
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int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr);
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int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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u32 intid, u32 *val);
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int kvm_register_vgic_device(unsigned long type);
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void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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int vgic_lazy_init(struct kvm *kvm);
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int vgic_init(struct kvm *kvm);
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void vgic_debug_init(struct kvm *kvm);
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void vgic_debug_destroy(struct kvm *kvm);
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bool lock_all_vcpus(struct kvm *kvm);
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void unlock_all_vcpus(struct kvm *kvm);
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static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
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{
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struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
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/*
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* num_pri_bits are initialized with HW supported values.
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* We can rely safely on num_pri_bits even if VM has not
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* restored ICC_CTLR_EL1 before restoring APnR registers.
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*/
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switch (cpu_if->num_pri_bits) {
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case 7: return 3;
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case 6: return 1;
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default: return 0;
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}
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}
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static inline bool
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vgic_v3_redist_region_full(struct vgic_redist_region *region)
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{
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if (!region->count)
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return false;
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return (region->free_index >= region->count);
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}
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struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rdregs);
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static inline size_t
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vgic_v3_rd_region_size(struct kvm *kvm, struct vgic_redist_region *rdreg)
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{
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if (!rdreg->count)
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return atomic_read(&kvm->online_vcpus) * KVM_VGIC_V3_REDIST_SIZE;
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else
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return rdreg->count * KVM_VGIC_V3_REDIST_SIZE;
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}
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struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
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u32 index);
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void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg);
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bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size);
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static inline bool vgic_dist_overlap(struct kvm *kvm, gpa_t base, size_t size)
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{
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struct vgic_dist *d = &kvm->arch.vgic;
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return (base + size > d->vgic_dist_base) &&
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(base < d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE);
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}
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bool vgic_lpis_enabled(struct kvm_vcpu *vcpu);
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int vgic_copy_lpi_list(struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr);
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int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
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u32 devid, u32 eventid, struct vgic_irq **irq);
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struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);
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int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi);
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void vgic_lpi_translation_cache_init(struct kvm *kvm);
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void vgic_lpi_translation_cache_destroy(struct kvm *kvm);
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void vgic_its_invalidate_cache(struct kvm *kvm);
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/* GICv4.1 MMIO interface */
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int vgic_its_inv_lpi(struct kvm *kvm, struct vgic_irq *irq);
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int vgic_its_invall(struct kvm_vcpu *vcpu);
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bool vgic_supports_direct_msis(struct kvm *kvm);
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int vgic_v4_init(struct kvm *kvm);
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void vgic_v4_teardown(struct kvm *kvm);
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void vgic_v4_configure_vsgis(struct kvm *kvm);
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void vgic_v4_get_vlpi_state(struct vgic_irq *irq, bool *val);
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int vgic_v4_request_vpe_irq(struct kvm_vcpu *vcpu, int irq);
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#endif
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