529 lines
12 KiB
C
529 lines
12 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "pci-bcm63xx.h"
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/*
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* swizzle 32bits data to return only the needed part
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*/
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static int postprocess_read(u32 data, int where, unsigned int size)
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{
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u32 ret;
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ret = 0;
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switch (size) {
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case 1:
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ret = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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ret = (data >> ((where & 3) << 3)) & 0xffff;
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break;
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case 4:
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ret = data;
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break;
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}
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return ret;
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}
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static int preprocess_write(u32 orig_data, u32 val, int where,
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unsigned int size)
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{
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u32 ret;
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ret = 0;
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switch (size) {
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case 1:
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ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 2:
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ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 4:
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ret = val;
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break;
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}
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return ret;
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}
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/*
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* setup hardware for a configuration cycle with given parameters
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*/
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static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
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unsigned int devfn, int where)
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{
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unsigned int slot, func, reg;
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u32 val;
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slot = PCI_SLOT(devfn);
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func = PCI_FUNC(devfn);
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reg = where >> 2;
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/* sanity check */
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if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
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return 1;
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if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
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return 1;
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if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
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return 1;
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/* ok, setup config access */
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val = (reg << MPI_L2PCFG_REG_SHIFT);
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val |= (func << MPI_L2PCFG_FUNC_SHIFT);
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val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
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val |= MPI_L2PCFG_CFG_USEREG_MASK;
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val |= MPI_L2PCFG_CFG_SEL_MASK;
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/* type 0 cycle for local bus, type 1 cycle for anything else */
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if (type != 0) {
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/* FIXME: how to specify bus ??? */
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val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
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}
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bcm_mpi_writel(val, MPI_L2PCFG_REG);
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return 0;
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}
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static int bcm63xx_do_cfg_read(int type, unsigned int busn,
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unsigned int devfn, int where, int size,
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u32 *val)
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{
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u32 data;
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/* two phase cycle, first we write address, then read data at
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* another location, caller already has a spinlock so no need
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* to add one here */
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if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
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return PCIBIOS_DEVICE_NOT_FOUND;
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iob();
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data = le32_to_cpu(__raw_readl(pci_iospace_start));
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/* restore IO space normal behaviour */
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bcm_mpi_writel(0, MPI_L2PCFG_REG);
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*val = postprocess_read(data, where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm63xx_do_cfg_write(int type, unsigned int busn,
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unsigned int devfn, int where, int size,
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u32 val)
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{
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u32 data;
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/* two phase cycle, first we write address, then write data to
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* another location, caller already has a spinlock so no need
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* to add one here */
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if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
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return PCIBIOS_DEVICE_NOT_FOUND;
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iob();
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data = le32_to_cpu(__raw_readl(pci_iospace_start));
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data = preprocess_write(data, val, where, size);
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__raw_writel(cpu_to_le32(data), pci_iospace_start);
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wmb();
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/* no way to know the access is done, we have to wait */
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udelay(500);
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/* restore IO space normal behaviour */
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bcm_mpi_writel(0, MPI_L2PCFG_REG);
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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int type;
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type = bus->parent ? 1 : 0;
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if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return bcm63xx_do_cfg_read(type, bus->number, devfn,
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where, size, val);
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}
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static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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int type;
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type = bus->parent ? 1 : 0;
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if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return bcm63xx_do_cfg_write(type, bus->number, devfn,
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where, size, val);
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}
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struct pci_ops bcm63xx_pci_ops = {
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.read = bcm63xx_pci_read,
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.write = bcm63xx_pci_write
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};
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#ifdef CONFIG_CARDBUS
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/*
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* emulate configuration read access on a cardbus bridge
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*/
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#define FAKE_CB_BRIDGE_SLOT 0x1e
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static int fake_cb_bridge_bus_number = -1;
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static struct {
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u16 pci_command;
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u8 cb_latency;
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u8 subordinate_busn;
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u8 cardbus_busn;
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u8 pci_busn;
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int bus_assigned;
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u16 bridge_control;
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u32 mem_base0;
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u32 mem_limit0;
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u32 mem_base1;
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u32 mem_limit1;
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u32 io_base0;
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u32 io_limit0;
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u32 io_base1;
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u32 io_limit1;
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} fake_cb_bridge_regs;
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static int fake_cb_bridge_read(int where, int size, u32 *val)
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{
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unsigned int reg;
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u32 data;
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data = 0;
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reg = where >> 2;
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switch (reg) {
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case (PCI_VENDOR_ID >> 2):
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case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
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/* create dummy vendor/device id from our cpu id */
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data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM;
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break;
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case (PCI_COMMAND >> 2):
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data = (PCI_STATUS_DEVSEL_SLOW << 16);
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data |= fake_cb_bridge_regs.pci_command;
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break;
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case (PCI_CLASS_REVISION >> 2):
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data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
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break;
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case (PCI_CACHE_LINE_SIZE >> 2):
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data = (PCI_HEADER_TYPE_CARDBUS << 16);
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break;
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case (PCI_INTERRUPT_LINE >> 2):
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/* bridge control */
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data = (fake_cb_bridge_regs.bridge_control << 16);
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/* pin:intA line:0xff */
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data |= (0x1 << 8) | 0xff;
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break;
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case (PCI_CB_PRIMARY_BUS >> 2):
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data = (fake_cb_bridge_regs.cb_latency << 24);
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data |= (fake_cb_bridge_regs.subordinate_busn << 16);
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data |= (fake_cb_bridge_regs.cardbus_busn << 8);
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data |= fake_cb_bridge_regs.pci_busn;
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break;
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case (PCI_CB_MEMORY_BASE_0 >> 2):
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data = fake_cb_bridge_regs.mem_base0;
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break;
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case (PCI_CB_MEMORY_LIMIT_0 >> 2):
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data = fake_cb_bridge_regs.mem_limit0;
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break;
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case (PCI_CB_MEMORY_BASE_1 >> 2):
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data = fake_cb_bridge_regs.mem_base1;
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break;
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case (PCI_CB_MEMORY_LIMIT_1 >> 2):
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data = fake_cb_bridge_regs.mem_limit1;
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break;
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case (PCI_CB_IO_BASE_0 >> 2):
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/* | 1 for 32bits io support */
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data = fake_cb_bridge_regs.io_base0 | 0x1;
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break;
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case (PCI_CB_IO_LIMIT_0 >> 2):
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data = fake_cb_bridge_regs.io_limit0;
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break;
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case (PCI_CB_IO_BASE_1 >> 2):
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/* | 1 for 32bits io support */
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data = fake_cb_bridge_regs.io_base1 | 0x1;
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break;
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case (PCI_CB_IO_LIMIT_1 >> 2):
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data = fake_cb_bridge_regs.io_limit1;
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break;
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}
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*val = postprocess_read(data, where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* emulate configuration write access on a cardbus bridge
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*/
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static int fake_cb_bridge_write(int where, int size, u32 val)
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{
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unsigned int reg;
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u32 data, tmp;
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int ret;
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ret = fake_cb_bridge_read((where & ~0x3), 4, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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data = preprocess_write(data, val, where, size);
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reg = where >> 2;
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switch (reg) {
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case (PCI_COMMAND >> 2):
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fake_cb_bridge_regs.pci_command = (data & 0xffff);
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break;
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case (PCI_CB_PRIMARY_BUS >> 2):
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fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
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fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
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fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
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fake_cb_bridge_regs.pci_busn = data & 0xff;
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if (fake_cb_bridge_regs.cardbus_busn)
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fake_cb_bridge_regs.bus_assigned = 1;
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break;
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case (PCI_INTERRUPT_LINE >> 2):
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tmp = (data >> 16) & 0xffff;
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/* disable memory prefetch support */
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tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
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tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
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fake_cb_bridge_regs.bridge_control = tmp;
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break;
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case (PCI_CB_MEMORY_BASE_0 >> 2):
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fake_cb_bridge_regs.mem_base0 = data;
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break;
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case (PCI_CB_MEMORY_LIMIT_0 >> 2):
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fake_cb_bridge_regs.mem_limit0 = data;
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break;
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case (PCI_CB_MEMORY_BASE_1 >> 2):
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fake_cb_bridge_regs.mem_base1 = data;
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break;
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case (PCI_CB_MEMORY_LIMIT_1 >> 2):
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fake_cb_bridge_regs.mem_limit1 = data;
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break;
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case (PCI_CB_IO_BASE_0 >> 2):
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fake_cb_bridge_regs.io_base0 = data;
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break;
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case (PCI_CB_IO_LIMIT_0 >> 2):
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fake_cb_bridge_regs.io_limit0 = data;
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break;
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case (PCI_CB_IO_BASE_1 >> 2):
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fake_cb_bridge_regs.io_base1 = data;
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break;
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case (PCI_CB_IO_LIMIT_1 >> 2):
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fake_cb_bridge_regs.io_limit1 = data;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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/* snoop access to slot 0x1e on root bus, we fake a cardbus
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* bridge at this location */
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if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
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fake_cb_bridge_bus_number = bus->number;
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return fake_cb_bridge_read(where, size, val);
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}
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/* a configuration cycle for the device behind the cardbus
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* bridge is actually done as a type 0 cycle on the primary
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* bus. This means that only one device can be on the cardbus
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* bus */
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if (fake_cb_bridge_regs.bus_assigned &&
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bus->number == fake_cb_bridge_regs.cardbus_busn &&
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PCI_SLOT(devfn) == 0)
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return bcm63xx_do_cfg_read(0, 0,
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PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
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where, size, val);
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
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fake_cb_bridge_bus_number = bus->number;
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return fake_cb_bridge_write(where, size, val);
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}
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if (fake_cb_bridge_regs.bus_assigned &&
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bus->number == fake_cb_bridge_regs.cardbus_busn &&
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PCI_SLOT(devfn) == 0)
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return bcm63xx_do_cfg_write(0, 0,
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PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
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where, size, val);
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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struct pci_ops bcm63xx_cb_ops = {
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.read = bcm63xx_cb_read,
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.write = bcm63xx_cb_write,
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};
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/*
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* only one IO window, so it cannot be shared by PCI and cardbus, use
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* fixup to choose and detect unhandled configuration
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*/
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static void bcm63xx_fixup(struct pci_dev *dev)
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{
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static int io_window = -1;
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int i, found, new_io_window;
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u32 val;
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/* look for any io resource */
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found = 0;
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
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found = 1;
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break;
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}
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}
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if (!found)
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return;
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/* skip our fake bus with only cardbus bridge on it */
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if (dev->bus->number == fake_cb_bridge_bus_number)
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return;
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/* find on which bus the device is */
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if (fake_cb_bridge_regs.bus_assigned &&
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dev->bus->number == fake_cb_bridge_regs.cardbus_busn &&
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PCI_SLOT(dev->devfn) == 0)
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new_io_window = 1;
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else
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new_io_window = 0;
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if (new_io_window == io_window)
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return;
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if (io_window != -1) {
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printk(KERN_ERR "bcm63xx: both PCI and cardbus devices "
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"need IO, which hardware cannot do\n");
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return;
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}
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printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n",
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(new_io_window == 0) ? "PCI" : "cardbus");
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val = bcm_mpi_readl(MPI_L2PIOREMAP_REG);
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if (io_window)
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val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
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else
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val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
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bcm_mpi_writel(val, MPI_L2PIOREMAP_REG);
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io_window = new_io_window;
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}
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DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
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#endif
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static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
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{
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switch (bus->number) {
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case PCIE_BUS_BRIDGE:
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return PCI_SLOT(devfn) == 0;
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case PCIE_BUS_DEVICE:
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if (PCI_SLOT(devfn) == 0)
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return bcm_pcie_readl(PCIE_DLSTATUS_REG)
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& DLSTATUS_PHYLINKUP;
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fallthrough;
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default:
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return false;
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}
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}
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static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 data;
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u32 reg = where & ~3;
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if (!bcm63xx_pcie_can_access(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (bus->number == PCIE_BUS_DEVICE)
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reg += PCIE_DEVICE_OFFSET;
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data = bcm_pcie_readl(reg);
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*val = postprocess_read(data, where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data;
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u32 reg = where & ~3;
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if (!bcm63xx_pcie_can_access(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (bus->number == PCIE_BUS_DEVICE)
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reg += PCIE_DEVICE_OFFSET;
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data = bcm_pcie_readl(reg);
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data = preprocess_write(data, val, where, size);
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bcm_pcie_writel(data, reg);
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return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
|
|
struct pci_ops bcm63xx_pcie_ops = {
|
|
.read = bcm63xx_pcie_read,
|
|
.write = bcm63xx_pcie_write
|
|
};
|