442 lines
11 KiB
C
442 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2013, Michael (Ellerman|Neuling), IBM Corporation.
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*/
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#define pr_fmt(fmt) "powernv: " fmt
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#include <linux/kernel.h>
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#include <linux/cpu.h>
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#include <linux/cpumask.h>
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#include <linux/device.h>
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#include <linux/gfp.h>
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#include <linux/smp.h>
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#include <linux/stop_machine.h>
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#include <asm/cputhreads.h>
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#include <asm/cpuidle.h>
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#include <asm/kvm_ppc.h>
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#include <asm/machdep.h>
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#include <asm/opal.h>
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#include <asm/smp.h>
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#include "subcore.h"
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#include "powernv.h"
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/*
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* Split/unsplit procedure:
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*
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* A core can be in one of three states, unsplit, 2-way split, and 4-way split.
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*
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* The mapping to subcores_per_core is simple:
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*
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* State | subcores_per_core
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* ------------|------------------
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* Unsplit | 1
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* 2-way split | 2
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* 4-way split | 4
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*
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* The core is split along thread boundaries, the mapping between subcores and
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* threads is as follows:
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*
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* Unsplit:
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* ----------------------------
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* Subcore | 0 |
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* ----------------------------
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* Thread | 0 1 2 3 4 5 6 7 |
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* ----------------------------
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*
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* 2-way split:
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* -------------------------------------
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* Subcore | 0 | 1 |
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* -------------------------------------
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* Thread | 0 1 2 3 | 4 5 6 7 |
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* -------------------------------------
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*
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* 4-way split:
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* -----------------------------------------
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* Subcore | 0 | 1 | 2 | 3 |
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* -----------------------------------------
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* Thread | 0 1 | 2 3 | 4 5 | 6 7 |
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* -----------------------------------------
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*
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*
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* Transitions
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* -----------
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*
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* It is not possible to transition between either of the split states, the
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* core must first be unsplit. The legal transitions are:
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*
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* ----------- ---------------
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* | | <----> | 2-way split |
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* | | ---------------
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* | Unsplit |
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* | | ---------------
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* | | <----> | 4-way split |
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* ----------- ---------------
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*
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* Unsplitting
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* -----------
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*
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* Unsplitting is the simpler procedure. It requires thread 0 to request the
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* unsplit while all other threads NAP.
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*
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* Thread 0 clears HID0_POWER8_DYNLPARDIS (Dynamic LPAR Disable). This tells
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* the hardware that if all threads except 0 are napping, the hardware should
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* unsplit the core.
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*
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* Non-zero threads are sent to a NAP loop, they don't exit the loop until they
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* see the core unsplit.
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*
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* Core 0 spins waiting for the hardware to see all the other threads napping
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* and perform the unsplit.
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*
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* Once thread 0 sees the unsplit, it IPIs the secondary threads to wake them
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* out of NAP. They will then see the core unsplit and exit the NAP loop.
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*
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* Splitting
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* ---------
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*
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* The basic splitting procedure is fairly straight forward. However it is
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* complicated by the fact that after the split occurs, the newly created
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* subcores are not in a fully initialised state.
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*
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* Most notably the subcores do not have the correct value for SDR1, which
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* means they must not be running in virtual mode when the split occurs. The
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* subcores have separate timebases SPRs but these are pre-synchronised by
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* opal.
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*
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* To begin with secondary threads are sent to an assembly routine. There they
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* switch to real mode, so they are immune to the uninitialised SDR1 value.
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* Once in real mode they indicate that they are in real mode, and spin waiting
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* to see the core split.
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*
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* Thread 0 waits to see that all secondaries are in real mode, and then begins
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* the splitting procedure. It firstly sets HID0_POWER8_DYNLPARDIS, which
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* prevents the hardware from unsplitting. Then it sets the appropriate HID bit
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* to request the split, and spins waiting to see that the split has happened.
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*
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* Concurrently the secondaries will notice the split. When they do they set up
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* their SPRs, notably SDR1, and then they can return to virtual mode and exit
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* the procedure.
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*/
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/* Initialised at boot by subcore_init() */
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static int subcores_per_core;
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/*
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* Used to communicate to offline cpus that we want them to pop out of the
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* offline loop and do a split or unsplit.
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*
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* 0 - no split happening
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* 1 - unsplit in progress
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* 2 - split to 2 in progress
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* 4 - split to 4 in progress
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*/
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static int new_split_mode;
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static cpumask_var_t cpu_offline_mask;
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struct split_state {
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u8 step;
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u8 master;
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};
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static DEFINE_PER_CPU(struct split_state, split_state);
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static void wait_for_sync_step(int step)
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{
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int i, cpu = smp_processor_id();
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for (i = cpu + 1; i < cpu + threads_per_core; i++)
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while(per_cpu(split_state, i).step < step)
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barrier();
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/* Order the wait loop vs any subsequent loads/stores. */
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mb();
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}
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static void update_hid_in_slw(u64 hid0)
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{
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u64 idle_states = pnv_get_supported_cpuidle_states();
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if (idle_states & OPAL_PM_WINKLE_ENABLED) {
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/* OPAL call to patch slw with the new HID0 value */
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u64 cpu_pir = hard_smp_processor_id();
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opal_slw_set_reg(cpu_pir, SPRN_HID0, hid0);
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}
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}
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static inline void update_power8_hid0(unsigned long hid0)
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{
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/*
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* The HID0 update on Power8 should at the very least be
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* preceded by a SYNC instruction followed by an ISYNC
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* instruction
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*/
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asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
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}
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static void unsplit_core(void)
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{
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u64 hid0, mask;
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int i, cpu;
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mask = HID0_POWER8_2LPARMODE | HID0_POWER8_4LPARMODE;
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cpu = smp_processor_id();
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if (cpu_thread_in_core(cpu) != 0) {
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while (mfspr(SPRN_HID0) & mask)
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power7_idle_type(PNV_THREAD_NAP);
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per_cpu(split_state, cpu).step = SYNC_STEP_UNSPLIT;
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return;
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}
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hid0 = mfspr(SPRN_HID0);
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hid0 &= ~HID0_POWER8_DYNLPARDIS;
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update_power8_hid0(hid0);
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update_hid_in_slw(hid0);
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while (mfspr(SPRN_HID0) & mask)
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cpu_relax();
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/* Wake secondaries out of NAP */
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for (i = cpu + 1; i < cpu + threads_per_core; i++)
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smp_send_reschedule(i);
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wait_for_sync_step(SYNC_STEP_UNSPLIT);
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}
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static void split_core(int new_mode)
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{
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struct { u64 value; u64 mask; } split_parms[2] = {
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{ HID0_POWER8_1TO2LPAR, HID0_POWER8_2LPARMODE },
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{ HID0_POWER8_1TO4LPAR, HID0_POWER8_4LPARMODE }
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};
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int i, cpu;
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u64 hid0;
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/* Convert new_mode (2 or 4) into an index into our parms array */
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i = (new_mode >> 1) - 1;
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BUG_ON(i < 0 || i > 1);
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cpu = smp_processor_id();
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if (cpu_thread_in_core(cpu) != 0) {
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split_core_secondary_loop(&per_cpu(split_state, cpu).step);
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return;
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}
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wait_for_sync_step(SYNC_STEP_REAL_MODE);
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/* Write new mode */
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hid0 = mfspr(SPRN_HID0);
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hid0 |= HID0_POWER8_DYNLPARDIS | split_parms[i].value;
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update_power8_hid0(hid0);
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update_hid_in_slw(hid0);
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/* Wait for it to happen */
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while (!(mfspr(SPRN_HID0) & split_parms[i].mask))
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cpu_relax();
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}
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static void cpu_do_split(int new_mode)
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{
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/*
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* At boot subcores_per_core will be 0, so we will always unsplit at
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* boot. In the usual case where the core is already unsplit it's a
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* nop, and this just ensures the kernel's notion of the mode is
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* consistent with the hardware.
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*/
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if (subcores_per_core != 1)
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unsplit_core();
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if (new_mode != 1)
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split_core(new_mode);
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mb();
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per_cpu(split_state, smp_processor_id()).step = SYNC_STEP_FINISHED;
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}
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bool cpu_core_split_required(void)
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{
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smp_rmb();
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if (!new_split_mode)
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return false;
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cpu_do_split(new_split_mode);
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return true;
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}
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void update_subcore_sibling_mask(void)
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{
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int cpu;
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/*
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* sibling mask for the first cpu. Left shift this by required bits
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* to get sibling mask for the rest of the cpus.
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*/
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int sibling_mask_first_cpu = (1 << threads_per_subcore) - 1;
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for_each_possible_cpu(cpu) {
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int tid = cpu_thread_in_core(cpu);
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int offset = (tid / threads_per_subcore) * threads_per_subcore;
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int mask = sibling_mask_first_cpu << offset;
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paca_ptrs[cpu]->subcore_sibling_mask = mask;
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}
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}
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static int cpu_update_split_mode(void *data)
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{
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int cpu, new_mode = *(int *)data;
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if (this_cpu_ptr(&split_state)->master) {
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new_split_mode = new_mode;
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smp_wmb();
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cpumask_andnot(cpu_offline_mask, cpu_present_mask,
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cpu_online_mask);
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/* This should work even though the cpu is offline */
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for_each_cpu(cpu, cpu_offline_mask)
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smp_send_reschedule(cpu);
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}
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cpu_do_split(new_mode);
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if (this_cpu_ptr(&split_state)->master) {
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/* Wait for all cpus to finish before we touch subcores_per_core */
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for_each_present_cpu(cpu) {
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if (cpu >= setup_max_cpus)
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break;
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while(per_cpu(split_state, cpu).step < SYNC_STEP_FINISHED)
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barrier();
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}
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new_split_mode = 0;
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/* Make the new mode public */
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subcores_per_core = new_mode;
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threads_per_subcore = threads_per_core / subcores_per_core;
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update_subcore_sibling_mask();
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/* Make sure the new mode is written before we exit */
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mb();
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}
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return 0;
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}
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static int set_subcores_per_core(int new_mode)
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{
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struct split_state *state;
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int cpu;
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if (kvm_hv_mode_active()) {
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pr_err("Unable to change split core mode while KVM active.\n");
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return -EBUSY;
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}
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/*
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* We are only called at boot, or from the sysfs write. If that ever
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* changes we'll need a lock here.
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*/
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BUG_ON(new_mode < 1 || new_mode > 4 || new_mode == 3);
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for_each_present_cpu(cpu) {
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state = &per_cpu(split_state, cpu);
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state->step = SYNC_STEP_INITIAL;
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state->master = 0;
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}
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cpus_read_lock();
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/* This cpu will update the globals before exiting stop machine */
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this_cpu_ptr(&split_state)->master = 1;
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/* Ensure state is consistent before we call the other cpus */
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mb();
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stop_machine_cpuslocked(cpu_update_split_mode, &new_mode,
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cpu_online_mask);
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cpus_read_unlock();
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return 0;
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}
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static ssize_t __used store_subcores_per_core(struct device *dev,
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struct device_attribute *attr, const char *buf,
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size_t count)
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{
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unsigned long val;
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int rc;
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/* We are serialised by the attribute lock */
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rc = sscanf(buf, "%lx", &val);
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if (rc != 1)
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return -EINVAL;
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switch (val) {
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case 1:
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case 2:
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case 4:
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if (subcores_per_core == val)
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/* Nothing to do */
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goto out;
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break;
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default:
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return -EINVAL;
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}
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rc = set_subcores_per_core(val);
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if (rc)
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return rc;
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out:
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return count;
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}
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static ssize_t show_subcores_per_core(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sprintf(buf, "%x\n", subcores_per_core);
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}
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static DEVICE_ATTR(subcores_per_core, 0644,
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show_subcores_per_core, store_subcores_per_core);
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static int subcore_init(void)
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{
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unsigned pvr_ver;
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pvr_ver = PVR_VER(mfspr(SPRN_PVR));
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if (pvr_ver != PVR_POWER8 &&
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pvr_ver != PVR_POWER8E &&
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pvr_ver != PVR_POWER8NVL)
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return 0;
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/*
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* We need all threads in a core to be present to split/unsplit so
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* continue only if max_cpus are aligned to threads_per_core.
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*/
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if (setup_max_cpus % threads_per_core)
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return 0;
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BUG_ON(!alloc_cpumask_var(&cpu_offline_mask, GFP_KERNEL));
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set_subcores_per_core(1);
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return device_create_file(cpu_subsys.dev_root,
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&dev_attr_subcores_per_core);
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}
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machine_device_initcall(powernv, subcore_init);
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