85 lines
3.8 KiB
C
85 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/compat.h>
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#include <linux/ptrace.h>
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#include <asm/cio.h>
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#include <asm/asm-offsets.h>
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#include "boot.h"
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#define CCW0(cmd, addr, cnt, flg) \
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{ .cmd_code = cmd, .cda = addr, .count = cnt, .flags = flg, }
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#define PSW_MASK_DISABLED (PSW_MASK_WAIT | PSW_MASK_EA | PSW_MASK_BA)
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struct ipl_lowcore {
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psw_t32 ipl_psw; /* 0x0000 */
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struct ccw0 ccwpgm[2]; /* 0x0008 */
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u8 fill[56]; /* 0x0018 */
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struct ccw0 ccwpgmcc[20]; /* 0x0050 */
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u8 pad_0xf0[0x01a0-0x00f0]; /* 0x00f0 */
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psw_t restart_psw; /* 0x01a0 */
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psw_t external_new_psw; /* 0x01b0 */
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psw_t svc_new_psw; /* 0x01c0 */
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psw_t program_new_psw; /* 0x01d0 */
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psw_t mcck_new_psw; /* 0x01e0 */
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psw_t io_new_psw; /* 0x01f0 */
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};
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/*
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* Initial lowcore for IPL: the first 24 bytes are loaded by IPL to
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* addresses 0-23 (a PSW and two CCWs). Bytes 24-79 are discarded.
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* The next 160 bytes are loaded to addresses 0x18-0xb7. They form
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* the continuation of the CCW program started by IPL and load the
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* range 0x0f0-0x730 from the image to the range 0x0f0-0x730 in
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* memory. At the end of the channel program the PSW at location 0 is
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* loaded.
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* Initial processing starts at 0x200 = iplstart.
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*
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* The restart psw points to iplstart which allows to load a kernel
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* image into memory and starting it by a psw restart on any cpu. All
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* other default psw new locations contain a disabled wait psw where
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* the address indicates which psw was loaded.
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*
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* Note that the 'file' utility can detect s390 kernel images. For
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* that to succeed the two initial CCWs, and the 0x40 fill bytes must
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* be present.
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*/
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static struct ipl_lowcore ipl_lowcore __used __section(".ipldata") = {
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.ipl_psw = { .mask = PSW32_MASK_BASE, .addr = PSW32_ADDR_AMODE | IPL_START },
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.ccwpgm = {
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[ 0] = CCW0(CCW_CMD_READ_IPL, 0x018, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[ 1] = CCW0(CCW_CMD_READ_IPL, 0x068, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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},
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.fill = {
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[ 0 ... 55] = 0x40,
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},
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.ccwpgmcc = {
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[ 0] = CCW0(CCW_CMD_READ_IPL, 0x0f0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[ 1] = CCW0(CCW_CMD_READ_IPL, 0x140, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[ 2] = CCW0(CCW_CMD_READ_IPL, 0x190, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[ 3] = CCW0(CCW_CMD_READ_IPL, 0x1e0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[ 4] = CCW0(CCW_CMD_READ_IPL, 0x230, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[ 5] = CCW0(CCW_CMD_READ_IPL, 0x280, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[ 6] = CCW0(CCW_CMD_READ_IPL, 0x2d0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[ 7] = CCW0(CCW_CMD_READ_IPL, 0x320, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[ 8] = CCW0(CCW_CMD_READ_IPL, 0x370, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[ 9] = CCW0(CCW_CMD_READ_IPL, 0x3c0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[10] = CCW0(CCW_CMD_READ_IPL, 0x410, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[11] = CCW0(CCW_CMD_READ_IPL, 0x460, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[12] = CCW0(CCW_CMD_READ_IPL, 0x4b0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[13] = CCW0(CCW_CMD_READ_IPL, 0x500, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[14] = CCW0(CCW_CMD_READ_IPL, 0x550, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[15] = CCW0(CCW_CMD_READ_IPL, 0x5a0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[16] = CCW0(CCW_CMD_READ_IPL, 0x5f0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[17] = CCW0(CCW_CMD_READ_IPL, 0x640, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[18] = CCW0(CCW_CMD_READ_IPL, 0x690, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
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[19] = CCW0(CCW_CMD_READ_IPL, 0x6e0, 0x50, CCW_FLAG_SLI),
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},
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.restart_psw = { .mask = 0, .addr = IPL_START, },
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.external_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_EXT_NEW_PSW, },
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.svc_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_SVC_NEW_PSW, },
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.program_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_PGM_NEW_PSW, },
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.mcck_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_MCK_NEW_PSW, },
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.io_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_IO_NEW_PSW, },
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};
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