99 lines
2.1 KiB
C
99 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* DMA coherent memory allocation.
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*
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* Copyright (C) 2002 - 2005 Tensilica Inc.
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* Copyright (C) 2015 Cadence Design Systems Inc.
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*
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* Based on version for i386.
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*
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* Chris Zankel <chris@zankel.net>
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* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
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*/
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#include <linux/dma-map-ops.h>
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#include <linux/dma-direct.h>
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#include <linux/gfp.h>
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#include <linux/highmem.h>
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#include <linux/mm.h>
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#include <linux/types.h>
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#include <asm/cacheflush.h>
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#include <asm/io.h>
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#include <asm/platform.h>
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static void do_cache_op(phys_addr_t paddr, size_t size,
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void (*fn)(unsigned long, unsigned long))
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{
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unsigned long off = paddr & (PAGE_SIZE - 1);
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unsigned long pfn = PFN_DOWN(paddr);
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struct page *page = pfn_to_page(pfn);
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if (!PageHighMem(page))
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fn((unsigned long)phys_to_virt(paddr), size);
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else
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while (size > 0) {
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size_t sz = min_t(size_t, size, PAGE_SIZE - off);
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void *vaddr = kmap_atomic(page);
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fn((unsigned long)vaddr + off, sz);
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kunmap_atomic(vaddr);
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off = 0;
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++page;
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size -= sz;
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}
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}
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_BIDIRECTIONAL:
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case DMA_FROM_DEVICE:
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do_cache_op(paddr, size, __invalidate_dcache_range);
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break;
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case DMA_NONE:
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BUG();
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break;
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default:
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break;
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}
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}
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_BIDIRECTIONAL:
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case DMA_TO_DEVICE:
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if (XCHAL_DCACHE_IS_WRITEBACK)
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do_cache_op(paddr, size, __flush_dcache_range);
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break;
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case DMA_NONE:
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BUG();
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break;
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default:
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break;
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}
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}
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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__invalidate_dcache_range((unsigned long)page_address(page), size);
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}
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/*
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* Memory caching is platform-dependent in noMMU xtensa configurations.
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* This function should be implemented in platform code in order to enable
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* coherent DMA memory operations when CONFIG_MMU is not enabled.
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*/
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#ifdef CONFIG_MMU
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void *arch_dma_set_uncached(void *p, size_t size)
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{
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return p + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR;
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}
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#endif /* CONFIG_MMU */
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