643 lines
17 KiB
C
643 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* pata_amd.c - AMD PATA for new ATA layer
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* (C) 2005-2006 Red Hat Inc
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*
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* Based on pata-sil680. Errata information is taken from data sheets
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* and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
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* claimed by sata-nv.c.
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*
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* TODO:
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* Variable system clock when/if it makes sense
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* Power management on ports
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*
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*
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* Documentation publicly available.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_amd"
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#define DRV_VERSION "0.4.1"
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/**
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* timing_setup - shared timing computation and load
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* @ap: ATA port being set up
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* @adev: drive being configured
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* @offset: port offset
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* @speed: target speed
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* @clock: clock multiplier (number of times 33MHz for this part)
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*
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* Perform the actual timing set up for Nvidia or AMD PATA devices.
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* The actual devices vary so they all call into this helper function
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* providing the clock multipler and offset (because AMD and Nvidia put
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* the ports at different locations).
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*/
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static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
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{
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static const unsigned char amd_cyc2udma[] = {
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6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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struct ata_device *peer = ata_dev_pair(adev);
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int dn = ap->port_no * 2 + adev->devno;
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struct ata_timing at, apeer;
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int T, UT;
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const int amd_clock = 33333; /* KHz. */
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u8 t;
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T = 1000000000 / amd_clock;
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UT = T;
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if (clock >= 2)
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UT = T / 2;
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if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
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dev_err(&pdev->dev, "unknown mode %d\n", speed);
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return;
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}
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if (peer) {
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/* This may be over conservative */
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if (ata_dma_enabled(peer)) {
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ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
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ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
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}
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ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
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ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
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}
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if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
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if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
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/*
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* Now do the setup work
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*/
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/* Configure the address set up timing */
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pci_read_config_byte(pdev, offset + 0x0C, &t);
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t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
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pci_write_config_byte(pdev, offset + 0x0C , t);
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/* Configure the 8bit I/O timing */
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pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
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((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));
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/* Drive timing */
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pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
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((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));
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switch (clock) {
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case 1:
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t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
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break;
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case 2:
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t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
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break;
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case 3:
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t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
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break;
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case 4:
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t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
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break;
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default:
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return;
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}
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/* UDMA timing */
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if (at.udma)
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pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
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}
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/**
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* amd_pre_reset - perform reset handling
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* @link: ATA link
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* @deadline: deadline jiffies for the operation
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*
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* Reset sequence checking enable bits to see which ports are
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* active.
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*/
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static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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static const struct pci_bits amd_enable_bits[] = {
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{ 0x40, 1, 0x02, 0x02 },
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{ 0x40, 1, 0x01, 0x01 }
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};
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
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return -ENOENT;
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return ata_sff_prereset(link, deadline);
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}
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/**
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* amd_cable_detect - report cable type
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* @ap: port
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*
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* AMD controller/BIOS setups record the cable type in word 0x42
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*/
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static int amd_cable_detect(struct ata_port *ap)
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{
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static const u32 bitmask[2] = {0x03, 0x0C};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 ata66;
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pci_read_config_byte(pdev, 0x42, &ata66);
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if (ata66 & bitmask[ap->port_no])
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return ATA_CBL_PATA80;
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return ATA_CBL_PATA40;
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}
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/**
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* amd_fifo_setup - set the PIO FIFO for ATA/ATAPI
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* @ap: ATA interface
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*
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* Set the PCI fifo for this device according to the devices present
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* on the bus at this point in time. We need to turn the post write buffer
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* off for ATAPI devices as we may need to issue a word sized write to the
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* device as the final I/O
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*/
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static void amd_fifo_setup(struct ata_port *ap)
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{
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struct ata_device *adev;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static const u8 fifobit[2] = { 0xC0, 0x30};
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u8 fifo = fifobit[ap->port_no];
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u8 r;
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ata_for_each_dev(adev, &ap->link, ENABLED) {
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if (adev->class == ATA_DEV_ATAPI)
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fifo = 0;
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}
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if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) /* FIFO is broken */
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fifo = 0;
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/* On the later chips the read prefetch bits become no-op bits */
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pci_read_config_byte(pdev, 0x41, &r);
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r &= ~fifobit[ap->port_no];
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r |= fifo;
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pci_write_config_byte(pdev, 0x41, r);
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}
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/**
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* amd33_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program the AMD registers for PIO mode.
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*/
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static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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amd_fifo_setup(ap);
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timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
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}
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static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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amd_fifo_setup(ap);
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timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
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}
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static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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amd_fifo_setup(ap);
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timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
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}
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static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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amd_fifo_setup(ap);
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timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
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}
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/**
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* amd33_set_dmamode - set initial DMA mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program the MWDMA/UDMA modes for the AMD and Nvidia
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* chipset.
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*/
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static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
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}
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static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
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}
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static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
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}
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static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
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}
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/* Both host-side and drive-side detection results are worthless on NV
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* PATAs. Ignore them and just follow what BIOS configured. Both the
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* current configuration in PCI config reg and ACPI GTM result are
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* cached during driver attach and are consulted to select transfer
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* mode.
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*/
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static unsigned int nv_mode_filter(struct ata_device *dev,
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unsigned int xfer_mask)
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{
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static const unsigned int udma_mask_map[] =
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{ ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
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ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
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struct ata_port *ap = dev->link->ap;
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char acpi_str[32] = "";
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u32 saved_udma, udma;
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const struct ata_acpi_gtm *gtm;
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unsigned int bios_limit = 0, acpi_limit = 0, limit;
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/* find out what BIOS configured */
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udma = saved_udma = (unsigned long)ap->host->private_data;
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if (ap->port_no == 0)
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udma >>= 16;
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if (dev->devno == 0)
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udma >>= 8;
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if ((udma & 0xc0) == 0xc0)
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bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
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/* consult ACPI GTM too */
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gtm = ata_acpi_init_gtm(ap);
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if (gtm) {
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acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
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snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
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gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
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}
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/* be optimistic, EH can take care of things if something goes wrong */
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limit = bios_limit | acpi_limit;
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/* If PIO or DMA isn't configured at all, don't limit. Let EH
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* handle it.
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*/
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if (!(limit & ATA_MASK_PIO))
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limit |= ATA_MASK_PIO;
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if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
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limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;
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/* PIO4, MWDMA2, UDMA2 should always be supported regardless of
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cable detection result */
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limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2);
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ata_port_dbg(ap,
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"nv_mode_filter: 0x%x&0x%x->0x%x, BIOS=0x%x (0x%x) ACPI=0x%x%s\n",
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xfer_mask, limit, xfer_mask & limit, bios_limit,
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saved_udma, acpi_limit, acpi_str);
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return xfer_mask & limit;
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}
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/**
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* nv_pre_reset - cable detection
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* @link: ATA link
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* @deadline: deadline jiffies for the operation
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*
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* Perform cable detection. The BIOS stores this in PCI config
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* space for us.
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*/
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static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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static const struct pci_bits nv_enable_bits[] = {
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{ 0x50, 1, 0x02, 0x02 },
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{ 0x50, 1, 0x01, 0x01 }
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};
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
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return -ENOENT;
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return ata_sff_prereset(link, deadline);
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}
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/**
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* nv100_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program the AMD registers for PIO mode.
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*/
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static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
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}
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static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
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}
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/**
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* nv100_set_dmamode - set initial DMA mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program the MWDMA/UDMA modes for the AMD and Nvidia
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* chipset.
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*/
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static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
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}
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static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
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}
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static void nv_host_stop(struct ata_host *host)
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{
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u32 udma = (unsigned long)host->private_data;
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/* restore PCI config register 0x60 */
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pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
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}
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static struct scsi_host_template amd_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static const struct ata_port_operations amd_base_port_ops = {
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.inherits = &ata_bmdma32_port_ops,
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.prereset = amd_pre_reset,
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};
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static struct ata_port_operations amd33_port_ops = {
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.inherits = &amd_base_port_ops,
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.cable_detect = ata_cable_40wire,
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.set_piomode = amd33_set_piomode,
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.set_dmamode = amd33_set_dmamode,
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};
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static struct ata_port_operations amd66_port_ops = {
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.inherits = &amd_base_port_ops,
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.cable_detect = ata_cable_unknown,
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.set_piomode = amd66_set_piomode,
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.set_dmamode = amd66_set_dmamode,
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};
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static struct ata_port_operations amd100_port_ops = {
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.inherits = &amd_base_port_ops,
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.cable_detect = ata_cable_unknown,
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.set_piomode = amd100_set_piomode,
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.set_dmamode = amd100_set_dmamode,
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};
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static struct ata_port_operations amd133_port_ops = {
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.inherits = &amd_base_port_ops,
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.cable_detect = amd_cable_detect,
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.set_piomode = amd133_set_piomode,
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.set_dmamode = amd133_set_dmamode,
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};
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static const struct ata_port_operations nv_base_port_ops = {
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.inherits = &ata_bmdma_port_ops,
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.cable_detect = ata_cable_ignore,
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.mode_filter = nv_mode_filter,
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.prereset = nv_pre_reset,
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.host_stop = nv_host_stop,
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};
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static struct ata_port_operations nv100_port_ops = {
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.inherits = &nv_base_port_ops,
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.set_piomode = nv100_set_piomode,
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.set_dmamode = nv100_set_dmamode,
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};
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static struct ata_port_operations nv133_port_ops = {
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.inherits = &nv_base_port_ops,
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.set_piomode = nv133_set_piomode,
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.set_dmamode = nv133_set_dmamode,
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};
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static void amd_clear_fifo(struct pci_dev *pdev)
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{
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u8 fifo;
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/* Disable the FIFO, the FIFO logic will re-enable it as
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appropriate */
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pci_read_config_byte(pdev, 0x41, &fifo);
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fifo &= 0x0F;
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pci_write_config_byte(pdev, 0x41, fifo);
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}
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static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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static const struct ata_port_info info[10] = {
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{ /* 0: AMD 7401 - no swdma */
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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.port_ops = &amd33_port_ops
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},
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{ /* 1: Early AMD7409 - no swdma */
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA4,
|
|
.port_ops = &amd66_port_ops
|
|
},
|
|
{ /* 2: AMD 7409 */
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA4,
|
|
.port_ops = &amd66_port_ops
|
|
},
|
|
{ /* 3: AMD 7411 */
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA5,
|
|
.port_ops = &amd100_port_ops
|
|
},
|
|
{ /* 4: AMD 7441 */
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA5,
|
|
.port_ops = &amd100_port_ops
|
|
},
|
|
{ /* 5: AMD 8111 - no swdma */
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA6,
|
|
.port_ops = &amd133_port_ops
|
|
},
|
|
{ /* 6: AMD 8111 UDMA 100 (Serenade) - no swdma */
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA5,
|
|
.port_ops = &amd133_port_ops
|
|
},
|
|
{ /* 7: Nvidia Nforce */
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA5,
|
|
.port_ops = &nv100_port_ops
|
|
},
|
|
{ /* 8: Nvidia Nforce2 and later - no swdma */
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA6,
|
|
.port_ops = &nv133_port_ops
|
|
},
|
|
{ /* 9: AMD CS5536 (Geode companion) */
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA5,
|
|
.port_ops = &amd100_port_ops
|
|
}
|
|
};
|
|
const struct ata_port_info *ppi[] = { NULL, NULL };
|
|
int type = id->driver_data;
|
|
void *hpriv = NULL;
|
|
u8 fifo;
|
|
int rc;
|
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION);
|
|
|
|
rc = pcim_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
pci_read_config_byte(pdev, 0x41, &fifo);
|
|
|
|
/* Check for AMD7409 without swdma errata and if found adjust type */
|
|
if (type == 1 && pdev->revision > 0x7)
|
|
type = 2;
|
|
|
|
/* Serenade ? */
|
|
if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
|
|
pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
|
|
type = 6; /* UDMA 100 only */
|
|
|
|
/*
|
|
* Okay, type is determined now. Apply type-specific workarounds.
|
|
*/
|
|
ppi[0] = &info[type];
|
|
|
|
if (type < 3)
|
|
ata_pci_bmdma_clear_simplex(pdev);
|
|
if (pdev->vendor == PCI_VENDOR_ID_AMD)
|
|
amd_clear_fifo(pdev);
|
|
/* Cable detection on Nvidia chips doesn't work too well,
|
|
* cache BIOS programmed UDMA mode.
|
|
*/
|
|
if (type == 7 || type == 8) {
|
|
u32 udma;
|
|
|
|
pci_read_config_dword(pdev, 0x60, &udma);
|
|
hpriv = (void *)(unsigned long)udma;
|
|
}
|
|
|
|
/* And fire it up */
|
|
return ata_pci_bmdma_init_one(pdev, ppi, &amd_sht, hpriv, 0);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int amd_reinit_one(struct pci_dev *pdev)
|
|
{
|
|
struct ata_host *host = pci_get_drvdata(pdev);
|
|
int rc;
|
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_AMD) {
|
|
amd_clear_fifo(pdev);
|
|
if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
|
|
pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
|
|
ata_pci_bmdma_clear_simplex(pdev);
|
|
}
|
|
ata_host_resume(host);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct pci_device_id amd[] = {
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_DEV_IDE), 9 },
|
|
|
|
{ },
|
|
};
|
|
|
|
static struct pci_driver amd_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = amd,
|
|
.probe = amd_init_one,
|
|
.remove = ata_pci_remove_one,
|
|
#ifdef CONFIG_PM_SLEEP
|
|
.suspend = ata_pci_device_suspend,
|
|
.resume = amd_reinit_one,
|
|
#endif
|
|
};
|
|
|
|
module_pci_driver(amd_pci_driver);
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, amd);
|
|
MODULE_VERSION(DRV_VERSION);
|