611 lines
16 KiB
C
611 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Linaro Limited
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,sm6375-dispcc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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DT_BI_TCXO,
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DT_GCC_DISP_GPLL0_CLK,
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DT_DSI0_PHY_PLL_OUT_BYTECLK,
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DT_DSI0_PHY_PLL_OUT_DSICLK,
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};
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enum {
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P_BI_TCXO,
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P_DISP_CC_PLL0_OUT_EVEN,
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P_DISP_CC_PLL0_OUT_MAIN,
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P_DSI0_PHY_PLL_OUT_BYTECLK,
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P_DSI0_PHY_PLL_OUT_DSICLK,
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P_GCC_DISP_GPLL0_CLK,
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};
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static struct pll_vco lucid_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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/* 615MHz */
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static const struct alpha_pll_config disp_cc_pll0_config = {
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.l = 0x20,
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.alpha = 0x800,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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.config_ctl_hi1_val = 0x329a299c,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x00000000,
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};
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static struct clk_alpha_pll disp_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_vco,
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.num_vco = ARRAY_SIZE(lucid_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_ops,
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},
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},
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};
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static const struct parent_map disp_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
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};
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static const struct clk_parent_data disp_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
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};
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static const struct parent_map disp_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
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{ P_GCC_DISP_GPLL0_CLK, 4 },
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{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
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};
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static const struct clk_parent_data disp_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &disp_cc_pll0.clkr.hw },
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{ .index = DT_GCC_DISP_GPLL0_CLK },
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{ .hw = &disp_cc_pll0.clkr.hw },
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};
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static const struct parent_map disp_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_GCC_DISP_GPLL0_CLK, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_2[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_GCC_DISP_GPLL0_CLK },
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};
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static const struct parent_map disp_cc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
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};
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static const struct clk_parent_data disp_cc_parent_data_3[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
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};
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static const struct parent_map disp_cc_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data disp_cc_parent_data_4[] = {
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{ .index = DT_BI_TCXO },
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(37500000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
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F(75000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
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.cmd_rcgr = 0x115c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_2,
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.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_ahb_clk_src",
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.parent_data = disp_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
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.cmd_rcgr = 0x10c4,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk_src",
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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.ops = &clk_byte2_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
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.cmd_rcgr = 0x10e0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_esc0_clk_src",
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
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F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
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F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
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F(373500000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
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F(470000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
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F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
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.cmd_rcgr = 0x107c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_mdp_clk_src",
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
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.cmd_rcgr = 0x1064,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_3,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_pclk0_clk_src",
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.parent_data = disp_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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.ops = &clk_pixel_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
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F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
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F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
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.cmd_rcgr = 0x1094,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_rot_clk_src",
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
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.cmd_rcgr = 0x10ac,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_4,
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.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_vsync_clk_src",
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.parent_data = disp_cc_parent_data_4,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
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.reg = 0x10dc,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "disp_cc_mdss_byte0_div_clk_src",
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.parent_hws = (const struct clk_hw*[]) {
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&disp_cc_mdss_byte0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_regmap_div_ops,
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},
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};
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static struct clk_branch disp_cc_mdss_ahb_clk = {
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.halt_reg = 0x104c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x104c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_byte0_clk = {
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.halt_reg = 0x102c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x102c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
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.halt_reg = 0x1030,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1030,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_intf_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_esc0_clk = {
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.halt_reg = 0x1034,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1034,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_esc0_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_esc0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_mdp_clk = {
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.halt_reg = 0x1010,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1010,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_mdp_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_mdp_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
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.halt_reg = 0x1020,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x1020,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_mdp_lut_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_mdp_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
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.halt_reg = 0x2004,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x2004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_non_gdsc_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_pclk0_clk = {
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.halt_reg = 0x1168,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1168,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_pclk0_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_pclk0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_rot_clk = {
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.halt_reg = 0x1018,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1018,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_rot_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_rot_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
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.halt_reg = 0x200c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x200c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_rscc_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
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.halt_reg = 0x2008,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x2008,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_rscc_vsync_clk",
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.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_vsync_clk = {
|
|
.halt_reg = 0x1028,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1028,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_vsync_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_sleep_clk = {
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_sleep_clk",
|
|
.flags = CLK_IS_CRITICAL,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_xo_clk = {
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_xo_clk",
|
|
.flags = CLK_IS_CRITICAL,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct gdsc mdss_gdsc = {
|
|
.gdscr = 0x1004,
|
|
.en_rest_wait_val = 0x2,
|
|
.en_few_wait_val = 0x2,
|
|
.clk_dis_wait_val = 0xf,
|
|
.pd = {
|
|
.name = "mdss_gdsc",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = HW_CTRL,
|
|
};
|
|
|
|
static struct clk_regmap *disp_cc_sm6375_clocks[] = {
|
|
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
|
|
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
|
|
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
|
|
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
|
|
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
|
|
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
|
|
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
|
|
[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
|
|
};
|
|
|
|
static const struct qcom_reset_map disp_cc_sm6375_resets[] = {
|
|
[DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
|
|
[DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
|
|
};
|
|
|
|
static struct gdsc *disp_cc_sm6375_gdscs[] = {
|
|
[MDSS_GDSC] = &mdss_gdsc,
|
|
};
|
|
|
|
static const struct regmap_config disp_cc_sm6375_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x10000,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct qcom_cc_desc disp_cc_sm6375_desc = {
|
|
.config = &disp_cc_sm6375_regmap_config,
|
|
.clks = disp_cc_sm6375_clocks,
|
|
.num_clks = ARRAY_SIZE(disp_cc_sm6375_clocks),
|
|
.resets = disp_cc_sm6375_resets,
|
|
.num_resets = ARRAY_SIZE(disp_cc_sm6375_resets),
|
|
.gdscs = disp_cc_sm6375_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(disp_cc_sm6375_gdscs),
|
|
};
|
|
|
|
static const struct of_device_id disp_cc_sm6375_match_table[] = {
|
|
{ .compatible = "qcom,sm6375-dispcc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, disp_cc_sm6375_match_table);
|
|
|
|
static int disp_cc_sm6375_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
|
|
regmap = qcom_cc_map(pdev, &disp_cc_sm6375_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
|
|
|
return qcom_cc_really_probe(pdev, &disp_cc_sm6375_desc, regmap);
|
|
}
|
|
|
|
static struct platform_driver disp_cc_sm6375_driver = {
|
|
.probe = disp_cc_sm6375_probe,
|
|
.driver = {
|
|
.name = "disp_cc-sm6375",
|
|
.of_match_table = disp_cc_sm6375_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init disp_cc_sm6375_init(void)
|
|
{
|
|
return platform_driver_register(&disp_cc_sm6375_driver);
|
|
}
|
|
subsys_initcall(disp_cc_sm6375_init);
|
|
|
|
static void __exit disp_cc_sm6375_exit(void)
|
|
{
|
|
platform_driver_unregister(&disp_cc_sm6375_driver);
|
|
}
|
|
module_exit(disp_cc_sm6375_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI DISPCC SM6375 Driver");
|
|
MODULE_LICENSE("GPL");
|