379 lines
11 KiB
C
379 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare eDMA PCIe driver
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*
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* Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <linux/dma/edma.h>
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#include <linux/pci-epf.h>
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#include <linux/msi.h>
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#include <linux/bitfield.h>
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#include "dw-edma-core.h"
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#define DW_PCIE_VSEC_DMA_ID 0x6
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#define DW_PCIE_VSEC_DMA_BAR GENMASK(10, 8)
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#define DW_PCIE_VSEC_DMA_MAP GENMASK(2, 0)
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#define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0)
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#define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16)
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#define DW_BLOCK(a, b, c) \
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{ \
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.bar = a, \
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.off = b, \
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.sz = c, \
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},
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struct dw_edma_block {
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enum pci_barno bar;
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off_t off;
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size_t sz;
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};
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struct dw_edma_pcie_data {
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/* eDMA registers location */
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struct dw_edma_block rg;
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/* eDMA memory linked list location */
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struct dw_edma_block ll_wr[EDMA_MAX_WR_CH];
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struct dw_edma_block ll_rd[EDMA_MAX_RD_CH];
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/* eDMA memory data location */
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struct dw_edma_block dt_wr[EDMA_MAX_WR_CH];
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struct dw_edma_block dt_rd[EDMA_MAX_RD_CH];
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/* Other */
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enum dw_edma_map_format mf;
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u8 irqs;
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u16 wr_ch_cnt;
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u16 rd_ch_cnt;
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};
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static const struct dw_edma_pcie_data snps_edda_data = {
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/* eDMA registers location */
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.rg.bar = BAR_0,
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.rg.off = 0x00001000, /* 4 Kbytes */
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.rg.sz = 0x00002000, /* 8 Kbytes */
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/* eDMA memory linked list location */
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.ll_wr = {
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/* Channel 0 - BAR 2, offset 0 Mbytes, size 2 Kbytes */
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DW_BLOCK(BAR_2, 0x00000000, 0x00000800)
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/* Channel 1 - BAR 2, offset 2 Mbytes, size 2 Kbytes */
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DW_BLOCK(BAR_2, 0x00200000, 0x00000800)
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},
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.ll_rd = {
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/* Channel 0 - BAR 2, offset 4 Mbytes, size 2 Kbytes */
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DW_BLOCK(BAR_2, 0x00400000, 0x00000800)
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/* Channel 1 - BAR 2, offset 6 Mbytes, size 2 Kbytes */
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DW_BLOCK(BAR_2, 0x00600000, 0x00000800)
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},
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/* eDMA memory data location */
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.dt_wr = {
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/* Channel 0 - BAR 2, offset 8 Mbytes, size 2 Kbytes */
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DW_BLOCK(BAR_2, 0x00800000, 0x00000800)
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/* Channel 1 - BAR 2, offset 9 Mbytes, size 2 Kbytes */
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DW_BLOCK(BAR_2, 0x00900000, 0x00000800)
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},
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.dt_rd = {
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/* Channel 0 - BAR 2, offset 10 Mbytes, size 2 Kbytes */
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DW_BLOCK(BAR_2, 0x00a00000, 0x00000800)
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/* Channel 1 - BAR 2, offset 11 Mbytes, size 2 Kbytes */
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DW_BLOCK(BAR_2, 0x00b00000, 0x00000800)
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},
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/* Other */
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.mf = EDMA_MF_EDMA_UNROLL,
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.irqs = 1,
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.wr_ch_cnt = 2,
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.rd_ch_cnt = 2,
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};
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static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr)
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{
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return pci_irq_vector(to_pci_dev(dev), nr);
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}
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static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct pci_bus_region region;
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struct resource res = {
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.flags = IORESOURCE_MEM,
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.start = cpu_addr,
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.end = cpu_addr,
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};
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pcibios_resource_to_bus(pdev->bus, ®ion, &res);
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return region.start;
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}
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static const struct dw_edma_core_ops dw_edma_pcie_core_ops = {
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.irq_vector = dw_edma_pcie_irq_vector,
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.pci_address = dw_edma_pcie_address,
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};
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static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev,
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struct dw_edma_pcie_data *pdata)
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{
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u32 val, map;
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u16 vsec;
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u64 off;
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vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS,
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DW_PCIE_VSEC_DMA_ID);
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if (!vsec)
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return;
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pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val);
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if (PCI_VNDR_HEADER_REV(val) != 0x00 ||
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PCI_VNDR_HEADER_LEN(val) != 0x18)
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return;
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pci_dbg(pdev, "Detected PCIe Vendor-Specific Extended Capability DMA\n");
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pci_read_config_dword(pdev, vsec + 0x8, &val);
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map = FIELD_GET(DW_PCIE_VSEC_DMA_MAP, val);
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if (map != EDMA_MF_EDMA_LEGACY &&
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map != EDMA_MF_EDMA_UNROLL &&
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map != EDMA_MF_HDMA_COMPAT)
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return;
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pdata->mf = map;
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pdata->rg.bar = FIELD_GET(DW_PCIE_VSEC_DMA_BAR, val);
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pci_read_config_dword(pdev, vsec + 0xc, &val);
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pdata->wr_ch_cnt = min_t(u16, pdata->wr_ch_cnt,
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FIELD_GET(DW_PCIE_VSEC_DMA_WR_CH, val));
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pdata->rd_ch_cnt = min_t(u16, pdata->rd_ch_cnt,
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FIELD_GET(DW_PCIE_VSEC_DMA_RD_CH, val));
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pci_read_config_dword(pdev, vsec + 0x14, &val);
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off = val;
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pci_read_config_dword(pdev, vsec + 0x10, &val);
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off <<= 32;
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off |= val;
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pdata->rg.off = off;
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}
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static int dw_edma_pcie_probe(struct pci_dev *pdev,
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const struct pci_device_id *pid)
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{
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struct dw_edma_pcie_data *pdata = (void *)pid->driver_data;
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struct dw_edma_pcie_data vsec_data;
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struct device *dev = &pdev->dev;
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struct dw_edma_chip *chip;
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int err, nr_irqs;
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int i, mask;
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/* Enable PCI device */
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err = pcim_enable_device(pdev);
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if (err) {
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pci_err(pdev, "enabling device failed\n");
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return err;
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}
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memcpy(&vsec_data, pdata, sizeof(struct dw_edma_pcie_data));
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/*
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* Tries to find if exists a PCIe Vendor-Specific Extended Capability
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* for the DMA, if one exists, then reconfigures it.
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*/
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dw_edma_pcie_get_vsec_dma_data(pdev, &vsec_data);
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/* Mapping PCI BAR regions */
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mask = BIT(vsec_data.rg.bar);
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for (i = 0; i < vsec_data.wr_ch_cnt; i++) {
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mask |= BIT(vsec_data.ll_wr[i].bar);
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mask |= BIT(vsec_data.dt_wr[i].bar);
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}
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for (i = 0; i < vsec_data.rd_ch_cnt; i++) {
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mask |= BIT(vsec_data.ll_rd[i].bar);
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mask |= BIT(vsec_data.dt_rd[i].bar);
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}
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err = pcim_iomap_regions(pdev, mask, pci_name(pdev));
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if (err) {
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pci_err(pdev, "eDMA BAR I/O remapping failed\n");
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return err;
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}
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pci_set_master(pdev);
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/* DMA configuration */
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err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
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if (err) {
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pci_err(pdev, "DMA mask 64 set failed\n");
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return err;
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}
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/* Data structure allocation */
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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/* IRQs allocation */
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nr_irqs = pci_alloc_irq_vectors(pdev, 1, vsec_data.irqs,
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PCI_IRQ_MSI | PCI_IRQ_MSIX);
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if (nr_irqs < 1) {
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pci_err(pdev, "fail to alloc IRQ vector (number of IRQs=%u)\n",
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nr_irqs);
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return -EPERM;
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}
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/* Data structure initialization */
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chip->dev = dev;
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chip->mf = vsec_data.mf;
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chip->nr_irqs = nr_irqs;
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chip->ops = &dw_edma_pcie_core_ops;
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chip->ll_wr_cnt = vsec_data.wr_ch_cnt;
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chip->ll_rd_cnt = vsec_data.rd_ch_cnt;
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chip->reg_base = pcim_iomap_table(pdev)[vsec_data.rg.bar];
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if (!chip->reg_base)
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return -ENOMEM;
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for (i = 0; i < chip->ll_wr_cnt; i++) {
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struct dw_edma_region *ll_region = &chip->ll_region_wr[i];
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struct dw_edma_region *dt_region = &chip->dt_region_wr[i];
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struct dw_edma_block *ll_block = &vsec_data.ll_wr[i];
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struct dw_edma_block *dt_block = &vsec_data.dt_wr[i];
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ll_region->vaddr.io = pcim_iomap_table(pdev)[ll_block->bar];
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if (!ll_region->vaddr.io)
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return -ENOMEM;
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ll_region->vaddr.io += ll_block->off;
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ll_region->paddr = pci_bus_address(pdev, ll_block->bar);
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ll_region->paddr += ll_block->off;
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ll_region->sz = ll_block->sz;
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dt_region->vaddr.io = pcim_iomap_table(pdev)[dt_block->bar];
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if (!dt_region->vaddr.io)
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return -ENOMEM;
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dt_region->vaddr.io += dt_block->off;
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dt_region->paddr = pci_bus_address(pdev, dt_block->bar);
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dt_region->paddr += dt_block->off;
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dt_region->sz = dt_block->sz;
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}
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for (i = 0; i < chip->ll_rd_cnt; i++) {
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struct dw_edma_region *ll_region = &chip->ll_region_rd[i];
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struct dw_edma_region *dt_region = &chip->dt_region_rd[i];
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struct dw_edma_block *ll_block = &vsec_data.ll_rd[i];
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struct dw_edma_block *dt_block = &vsec_data.dt_rd[i];
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ll_region->vaddr.io = pcim_iomap_table(pdev)[ll_block->bar];
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if (!ll_region->vaddr.io)
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return -ENOMEM;
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ll_region->vaddr.io += ll_block->off;
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ll_region->paddr = pci_bus_address(pdev, ll_block->bar);
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ll_region->paddr += ll_block->off;
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ll_region->sz = ll_block->sz;
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dt_region->vaddr.io = pcim_iomap_table(pdev)[dt_block->bar];
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if (!dt_region->vaddr.io)
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return -ENOMEM;
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dt_region->vaddr.io += dt_block->off;
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dt_region->paddr = pci_bus_address(pdev, dt_block->bar);
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dt_region->paddr += dt_block->off;
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dt_region->sz = dt_block->sz;
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}
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/* Debug info */
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if (chip->mf == EDMA_MF_EDMA_LEGACY)
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pci_dbg(pdev, "Version:\teDMA Port Logic (0x%x)\n", chip->mf);
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else if (chip->mf == EDMA_MF_EDMA_UNROLL)
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pci_dbg(pdev, "Version:\teDMA Unroll (0x%x)\n", chip->mf);
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else if (chip->mf == EDMA_MF_HDMA_COMPAT)
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pci_dbg(pdev, "Version:\tHDMA Compatible (0x%x)\n", chip->mf);
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else
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pci_dbg(pdev, "Version:\tUnknown (0x%x)\n", chip->mf);
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pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p)\n",
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vsec_data.rg.bar, vsec_data.rg.off, vsec_data.rg.sz,
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chip->reg_base);
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for (i = 0; i < chip->ll_wr_cnt; i++) {
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pci_dbg(pdev, "L. List:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
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i, vsec_data.ll_wr[i].bar,
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vsec_data.ll_wr[i].off, chip->ll_region_wr[i].sz,
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chip->ll_region_wr[i].vaddr.io, &chip->ll_region_wr[i].paddr);
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pci_dbg(pdev, "Data:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
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i, vsec_data.dt_wr[i].bar,
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vsec_data.dt_wr[i].off, chip->dt_region_wr[i].sz,
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chip->dt_region_wr[i].vaddr.io, &chip->dt_region_wr[i].paddr);
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}
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for (i = 0; i < chip->ll_rd_cnt; i++) {
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pci_dbg(pdev, "L. List:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
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i, vsec_data.ll_rd[i].bar,
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vsec_data.ll_rd[i].off, chip->ll_region_rd[i].sz,
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chip->ll_region_rd[i].vaddr.io, &chip->ll_region_rd[i].paddr);
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pci_dbg(pdev, "Data:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
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i, vsec_data.dt_rd[i].bar,
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vsec_data.dt_rd[i].off, chip->dt_region_rd[i].sz,
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chip->dt_region_rd[i].vaddr.io, &chip->dt_region_rd[i].paddr);
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}
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pci_dbg(pdev, "Nr. IRQs:\t%u\n", chip->nr_irqs);
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/* Validating if PCI interrupts were enabled */
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if (!pci_dev_msi_enabled(pdev)) {
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pci_err(pdev, "enable interrupt failed\n");
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return -EPERM;
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}
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/* Starting eDMA driver */
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err = dw_edma_probe(chip);
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if (err) {
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pci_err(pdev, "eDMA probe failed\n");
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return err;
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}
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/* Saving data structure reference */
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pci_set_drvdata(pdev, chip);
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return 0;
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}
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static void dw_edma_pcie_remove(struct pci_dev *pdev)
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{
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struct dw_edma_chip *chip = pci_get_drvdata(pdev);
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int err;
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/* Stopping eDMA driver */
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err = dw_edma_remove(chip);
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if (err)
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pci_warn(pdev, "can't remove device properly: %d\n", err);
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/* Freeing IRQs */
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pci_free_irq_vectors(pdev);
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}
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static const struct pci_device_id dw_edma_pcie_id_table[] = {
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{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);
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static struct pci_driver dw_edma_pcie_driver = {
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.name = "dw-edma-pcie",
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.id_table = dw_edma_pcie_id_table,
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.probe = dw_edma_pcie_probe,
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.remove = dw_edma_pcie_remove,
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};
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module_pci_driver(dw_edma_pcie_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Synopsys DesignWare eDMA PCIe driver");
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MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");
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