222 lines
6.1 KiB
C
222 lines
6.1 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_ATOMBIOS_H__
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#define __AMDGPU_ATOMBIOS_H__
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struct atom_clock_dividers {
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u32 post_div;
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union {
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struct {
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#ifdef __BIG_ENDIAN
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u32 reserved : 6;
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u32 whole_fb_div : 12;
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u32 frac_fb_div : 14;
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#else
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u32 frac_fb_div : 14;
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u32 whole_fb_div : 12;
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u32 reserved : 6;
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#endif
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};
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u32 fb_div;
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};
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u32 ref_div;
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bool enable_post_div;
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bool enable_dithen;
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u32 vco_mode;
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u32 real_clock;
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/* added for CI */
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u32 post_divider;
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u32 flags;
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};
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struct atom_mpll_param {
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union {
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struct {
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#ifdef __BIG_ENDIAN
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u32 reserved : 8;
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u32 clkfrac : 12;
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u32 clkf : 12;
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#else
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u32 clkf : 12;
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u32 clkfrac : 12;
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u32 reserved : 8;
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#endif
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};
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u32 fb_div;
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};
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u32 post_div;
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u32 bwcntl;
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u32 dll_speed;
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u32 vco_mode;
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u32 yclk_sel;
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u32 qdr;
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u32 half_rate;
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};
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#define MEM_TYPE_GDDR5 0x50
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#define MEM_TYPE_GDDR4 0x40
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#define MEM_TYPE_GDDR3 0x30
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#define MEM_TYPE_DDR2 0x20
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#define MEM_TYPE_GDDR1 0x10
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#define MEM_TYPE_DDR3 0xb0
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#define MEM_TYPE_MASK 0xf0
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struct atom_memory_info {
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u8 mem_vendor;
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u8 mem_type;
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};
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#define MAX_AC_TIMING_ENTRIES 16
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struct atom_memory_clock_range_table
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{
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u8 num_entries;
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u8 rsv[3];
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u32 mclk[MAX_AC_TIMING_ENTRIES];
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};
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#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
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#define VBIOS_MAX_AC_TIMING_ENTRIES 20
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struct atom_mc_reg_entry {
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u32 mclk_max;
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u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
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};
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struct atom_mc_register_address {
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u16 s1;
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u8 pre_reg_data;
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};
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struct atom_mc_reg_table {
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u8 last;
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u8 num_entries;
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struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
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struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
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};
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#define MAX_VOLTAGE_ENTRIES 32
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struct atom_voltage_table_entry
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{
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u16 value;
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u32 smio_low;
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};
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struct atom_voltage_table
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{
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u32 count;
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u32 mask_low;
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u32 phase_delay;
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struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
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};
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struct amdgpu_gpio_rec
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amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
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u8 id);
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struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
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uint8_t id);
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void amdgpu_atombios_i2c_init(struct amdgpu_device *adev);
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bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev);
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bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev);
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int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev);
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int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev);
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int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev);
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bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
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struct amdgpu_atom_ss *ss,
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int id, u32 clock);
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int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
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u8 clock_type,
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u32 clock,
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bool strobe_mode,
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struct atom_clock_dividers *dividers);
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#ifdef CONFIG_DRM_AMDGPU_SI
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int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
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u32 clock,
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bool strobe_mode,
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struct atom_mpll_param *mpll_param);
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void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
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u32 eng_clock, u32 mem_clock);
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bool
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amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
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u8 voltage_type, u8 voltage_mode);
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int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
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u8 voltage_type, u8 voltage_mode,
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struct atom_voltage_table *voltage_table);
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int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
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u8 module_index,
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struct atom_mc_reg_table *reg_table);
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int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
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u16 voltage_id, u16 *voltage);
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int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
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u16 *voltage,
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u16 leakage_idx);
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void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
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u16 *vddc, u16 *vddci, u16 *mvdd);
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int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
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u8 voltage_type,
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u8 *svd_gpio_id, u8 *svc_gpio_id);
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#endif
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bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev);
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void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
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void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
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bool hung);
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void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device *adev,
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u32 backlight_level);
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bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
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void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
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int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
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u8 clock_type,
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u32 clock,
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bool strobe_mode,
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struct atom_clock_dividers *dividers);
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int amdgpu_atombios_get_data_table(struct amdgpu_device *adev,
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uint32_t table,
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uint16_t *size,
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uint8_t *frev,
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uint8_t *crev,
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uint8_t **addr);
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void amdgpu_atombios_fini(struct amdgpu_device *adev);
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int amdgpu_atombios_init(struct amdgpu_device *adev);
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#endif
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