1075 lines
28 KiB
C
1075 lines
28 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include <linux/pci.h>
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#include <drm/drm_cache.h>
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#include "amdgpu.h"
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#include "amdgpu_atomfirmware.h"
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#include "gmc_v11_0.h"
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#include "umc_v8_10.h"
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#include "athub/athub_3_0_0_sh_mask.h"
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#include "athub/athub_3_0_0_offset.h"
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#include "dcn/dcn_3_2_0_offset.h"
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#include "dcn/dcn_3_2_0_sh_mask.h"
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#include "oss/osssys_6_0_0_offset.h"
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#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
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#include "navi10_enum.h"
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#include "soc15.h"
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#include "soc15d.h"
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#include "soc15_common.h"
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#include "nbio_v4_3.h"
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#include "gfxhub_v3_0.h"
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#include "gfxhub_v3_0_3.h"
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#include "mmhub_v3_0.h"
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#include "mmhub_v3_0_1.h"
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#include "mmhub_v3_0_2.h"
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#include "athub_v3_0.h"
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static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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return 0;
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}
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static int
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gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src, unsigned type,
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enum amdgpu_interrupt_state state)
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{
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switch (state) {
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case AMDGPU_IRQ_STATE_DISABLE:
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/* MM HUB */
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amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
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/* GFX HUB */
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/* This works because this interrupt is only
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* enabled at init/resume and disabled in
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* fini/suspend, so the overall state doesn't
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* change over the course of suspend/resume.
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*/
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if (!adev->in_s0ix)
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amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
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break;
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case AMDGPU_IRQ_STATE_ENABLE:
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/* MM HUB */
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amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
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/* GFX HUB */
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/* This works because this interrupt is only
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* enabled at init/resume and disabled in
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* fini/suspend, so the overall state doesn't
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* change over the course of suspend/resume.
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*/
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if (!adev->in_s0ix)
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amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
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break;
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default:
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break;
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}
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return 0;
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}
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static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
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uint32_t status = 0;
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u64 addr;
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addr = (u64)entry->src_data[0] << 12;
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addr |= ((u64)entry->src_data[1] & 0xf) << 44;
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if (!amdgpu_sriov_vf(adev)) {
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/*
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* Issue a dummy read to wait for the status register to
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* be updated to avoid reading an incorrect value due to
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* the new fast GRBM interface.
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*/
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if (entry->vmid_src == AMDGPU_GFXHUB_0)
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RREG32(hub->vm_l2_pro_fault_status);
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status = RREG32(hub->vm_l2_pro_fault_status);
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WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
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}
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if (printk_ratelimit()) {
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struct amdgpu_task_info task_info;
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memset(&task_info, 0, sizeof(struct amdgpu_task_info));
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amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
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dev_err(adev->dev,
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"[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
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"for process %s pid %d thread %s pid %d)\n",
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entry->vmid_src ? "mmhub" : "gfxhub",
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entry->src_id, entry->ring_id, entry->vmid,
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entry->pasid, task_info.process_name, task_info.tgid,
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task_info.task_name, task_info.pid);
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dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
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addr, entry->client_id);
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if (!amdgpu_sriov_vf(adev))
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hub->vmhub_funcs->print_l2_protection_fault_status(adev, status);
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}
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return 0;
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}
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static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = {
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.set = gmc_v11_0_vm_fault_interrupt_state,
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.process = gmc_v11_0_process_interrupt,
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};
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static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = {
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.set = gmc_v11_0_ecc_interrupt_state,
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.process = amdgpu_umc_process_ecc_irq,
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};
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static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev)
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{
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adev->gmc.vm_fault.num_types = 1;
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adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs;
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if (!amdgpu_sriov_vf(adev)) {
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adev->gmc.ecc_irq.num_types = 1;
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adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs;
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}
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}
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/**
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* gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore
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*
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* @adev: amdgpu_device pointer
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* @vmhub: vmhub type
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*
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*/
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static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev,
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uint32_t vmhub)
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{
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return ((vmhub == AMDGPU_MMHUB_0) &&
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(!amdgpu_sriov_vf(adev)));
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}
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static bool gmc_v11_0_get_vmid_pasid_mapping_info(
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struct amdgpu_device *adev,
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uint8_t vmid, uint16_t *p_pasid)
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{
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*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
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return !!(*p_pasid);
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}
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/*
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* GART
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* VMID 0 is the physical GPU addresses as used by the kernel.
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* VMIDs 1-15 are used for userspace clients and are handled
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* by the amdgpu vm/hsa code.
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*/
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static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
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unsigned int vmhub, uint32_t flush_type)
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{
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bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub);
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struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
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u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
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u32 tmp;
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/* Use register 17 for GART */
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const unsigned eng = 17;
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unsigned int i;
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unsigned char hub_ip = 0;
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hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
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GC_HWIP : MMHUB_HWIP;
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spin_lock(&adev->gmc.invalidate_lock);
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/*
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* It may lose gpuvm invalidate acknowldege state across power-gating
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* off cycle, add semaphore acquire before invalidation and semaphore
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* release after invalidation to avoid entering power gated state
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* to WA the Issue
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*/
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/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
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if (use_semaphore) {
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for (i = 0; i < adev->usec_timeout; i++) {
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/* a read return value of 1 means semaphore acuqire */
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tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
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hub->eng_distance * eng, hub_ip);
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if (tmp & 0x1)
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break;
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udelay(1);
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}
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if (i >= adev->usec_timeout)
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DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
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}
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WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip);
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/* Wait for ACK with a delay.*/
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
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hub->eng_distance * eng, hub_ip);
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tmp &= 1 << vmid;
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if (tmp)
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break;
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udelay(1);
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}
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/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
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if (use_semaphore)
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/*
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* add semaphore release after invalidation,
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* write with 0 means semaphore release
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*/
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WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
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hub->eng_distance * eng, 0, hub_ip);
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/* Issue additional private vm invalidation to MMHUB */
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if ((vmhub != AMDGPU_GFXHUB_0) &&
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(hub->vm_l2_bank_select_reserved_cid2) &&
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!amdgpu_sriov_vf(adev)) {
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inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
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/* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */
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inv_req |= (1 << 25);
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/* Issue private invalidation */
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WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req);
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/* Read back to ensure invalidation is done*/
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RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
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}
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spin_unlock(&adev->gmc.invalidate_lock);
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if (i < adev->usec_timeout)
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return;
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DRM_ERROR("Timeout waiting for VM flush ACK!\n");
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}
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/**
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* gmc_v11_0_flush_gpu_tlb - gart tlb flush callback
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*
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* @adev: amdgpu_device pointer
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* @vmid: vm instance to flush
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*
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* Flush the TLB for the requested page table.
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*/
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static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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uint32_t vmhub, uint32_t flush_type)
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{
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if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron)
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return;
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/* flush hdp cache */
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adev->hdp.funcs->flush_hdp(adev, NULL);
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/* For SRIOV run time, driver shouldn't access the register through MMIO
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* Directly use kiq to do the vm invalidation instead
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*/
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if ((adev->gfx.kiq.ring.sched.ready || adev->mes.ring.sched.ready) &&
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(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
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struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
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const unsigned eng = 17;
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u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
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u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
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u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
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amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
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1 << vmid);
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return;
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}
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mutex_lock(&adev->mman.gtt_window_lock);
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gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0);
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mutex_unlock(&adev->mman.gtt_window_lock);
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return;
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}
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/**
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* gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid
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*
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* @adev: amdgpu_device pointer
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* @pasid: pasid to be flush
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*
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* Flush the TLB for the requested pasid.
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*/
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static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
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uint16_t pasid, uint32_t flush_type,
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bool all_hub)
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{
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int vmid, i;
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signed long r;
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uint32_t seq;
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uint16_t queried_pasid;
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bool ret;
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struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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if (amdgpu_emu_mode == 0 && ring->sched.ready) {
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spin_lock(&adev->gfx.kiq.ring_lock);
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/* 2 dwords flush + 8 dwords fence */
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amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
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kiq->pmf->kiq_invalidate_tlbs(ring,
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pasid, flush_type, all_hub);
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r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
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if (r) {
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amdgpu_ring_undo(ring);
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spin_unlock(&adev->gfx.kiq.ring_lock);
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return -ETIME;
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}
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amdgpu_ring_commit(ring);
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spin_unlock(&adev->gfx.kiq.ring_lock);
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r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
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if (r < 1) {
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dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
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return -ETIME;
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}
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return 0;
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}
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for (vmid = 1; vmid < 16; vmid++) {
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ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid,
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&queried_pasid);
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if (ret && queried_pasid == pasid) {
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if (all_hub) {
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for (i = 0; i < adev->num_vmhubs; i++)
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gmc_v11_0_flush_gpu_tlb(adev, vmid,
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i, flush_type);
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} else {
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gmc_v11_0_flush_gpu_tlb(adev, vmid,
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AMDGPU_GFXHUB_0, flush_type);
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}
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}
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}
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return 0;
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}
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static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
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unsigned vmid, uint64_t pd_addr)
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{
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bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
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unsigned eng = ring->vm_inv_eng;
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/*
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* It may lose gpuvm invalidate acknowldege state across power-gating
|
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* off cycle, add semaphore acquire before invalidation and semaphore
|
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* release after invalidation to avoid entering power gated state
|
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* to WA the Issue
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*/
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/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
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if (use_semaphore)
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/* a read return value of 1 means semaphore acuqire */
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amdgpu_ring_emit_reg_wait(ring,
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hub->vm_inv_eng0_sem +
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hub->eng_distance * eng, 0x1, 0x1);
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amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
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(hub->ctx_addr_distance * vmid),
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lower_32_bits(pd_addr));
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amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
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(hub->ctx_addr_distance * vmid),
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upper_32_bits(pd_addr));
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amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
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hub->eng_distance * eng,
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hub->vm_inv_eng0_ack +
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hub->eng_distance * eng,
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req, 1 << vmid);
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/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
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if (use_semaphore)
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/*
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* add semaphore release after invalidation,
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* write with 0 means semaphore release
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*/
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amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
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hub->eng_distance * eng, 0);
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return pd_addr;
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}
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static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
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unsigned pasid)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t reg;
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/* MES fw manages IH_VMID_x_LUT updating */
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if (ring->is_mes_queue)
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return;
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if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
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reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
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else
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reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
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amdgpu_ring_emit_wreg(ring, reg, pasid);
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}
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/*
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* PTE format:
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* 63:59 reserved
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* 58:57 reserved
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* 56 F
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* 55 L
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* 54 reserved
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|
* 53:52 SW
|
|
* 51 T
|
|
* 50:48 mtype
|
|
* 47:12 4k physical page base address
|
|
* 11:7 fragment
|
|
* 6 write
|
|
* 5 read
|
|
* 4 exe
|
|
* 3 Z
|
|
* 2 snooped
|
|
* 1 system
|
|
* 0 valid
|
|
*
|
|
* PDE format:
|
|
* 63:59 block fragment size
|
|
* 58:55 reserved
|
|
* 54 P
|
|
* 53:48 reserved
|
|
* 47:6 physical base address of PD or PTE
|
|
* 5:3 reserved
|
|
* 2 C
|
|
* 1 system
|
|
* 0 valid
|
|
*/
|
|
|
|
static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
|
|
{
|
|
switch (flags) {
|
|
case AMDGPU_VM_MTYPE_DEFAULT:
|
|
return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
|
|
case AMDGPU_VM_MTYPE_NC:
|
|
return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
|
|
case AMDGPU_VM_MTYPE_WC:
|
|
return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
|
|
case AMDGPU_VM_MTYPE_CC:
|
|
return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
|
|
case AMDGPU_VM_MTYPE_UC:
|
|
return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
|
|
default:
|
|
return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
|
|
}
|
|
}
|
|
|
|
static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level,
|
|
uint64_t *addr, uint64_t *flags)
|
|
{
|
|
if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
|
|
*addr = adev->vm_manager.vram_base_offset + *addr -
|
|
adev->gmc.vram_start;
|
|
BUG_ON(*addr & 0xFFFF00000000003FULL);
|
|
|
|
if (!adev->gmc.translate_further)
|
|
return;
|
|
|
|
if (level == AMDGPU_VM_PDB1) {
|
|
/* Set the block fragment size */
|
|
if (!(*flags & AMDGPU_PDE_PTE))
|
|
*flags |= AMDGPU_PDE_BFS(0x9);
|
|
|
|
} else if (level == AMDGPU_VM_PDB0) {
|
|
if (*flags & AMDGPU_PDE_PTE)
|
|
*flags &= ~AMDGPU_PDE_PTE;
|
|
else
|
|
*flags |= AMDGPU_PTE_TF;
|
|
}
|
|
}
|
|
|
|
static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
|
|
struct amdgpu_bo_va_mapping *mapping,
|
|
uint64_t *flags)
|
|
{
|
|
struct amdgpu_bo *bo = mapping->bo_va->base.bo;
|
|
|
|
*flags &= ~AMDGPU_PTE_EXECUTABLE;
|
|
*flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
|
|
|
|
*flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
|
|
*flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
|
|
|
|
*flags &= ~AMDGPU_PTE_NOALLOC;
|
|
*flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
|
|
|
|
if (mapping->flags & AMDGPU_PTE_PRT) {
|
|
*flags |= AMDGPU_PTE_PRT;
|
|
*flags |= AMDGPU_PTE_SNOOPED;
|
|
*flags |= AMDGPU_PTE_LOG;
|
|
*flags |= AMDGPU_PTE_SYSTEM;
|
|
*flags &= ~AMDGPU_PTE_VALID;
|
|
}
|
|
|
|
if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
|
|
AMDGPU_GEM_CREATE_UNCACHED))
|
|
*flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
|
|
AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
|
|
}
|
|
|
|
static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev)
|
|
{
|
|
u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL);
|
|
unsigned size;
|
|
|
|
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
|
size = AMDGPU_VBIOS_VGA_ALLOCATION;
|
|
} else {
|
|
u32 viewport;
|
|
u32 pitch;
|
|
|
|
viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
|
|
pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH);
|
|
size = (REG_GET_FIELD(viewport,
|
|
HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
|
|
REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
|
|
4);
|
|
}
|
|
|
|
return size;
|
|
}
|
|
|
|
static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {
|
|
.flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb,
|
|
.flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid,
|
|
.emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb,
|
|
.emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping,
|
|
.map_mtype = gmc_v11_0_map_mtype,
|
|
.get_vm_pde = gmc_v11_0_get_vm_pde,
|
|
.get_vm_pte = gmc_v11_0_get_vm_pte,
|
|
.get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size,
|
|
};
|
|
|
|
static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev)
|
|
{
|
|
adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs;
|
|
}
|
|
|
|
static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev)
|
|
{
|
|
switch (adev->ip_versions[UMC_HWIP][0]) {
|
|
case IP_VERSION(8, 10, 0):
|
|
adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM;
|
|
adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM;
|
|
adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
|
|
adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET;
|
|
adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM;
|
|
if (adev->umc.node_inst_num == 4)
|
|
adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0];
|
|
else
|
|
adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0];
|
|
adev->umc.ras = &umc_v8_10_ras;
|
|
break;
|
|
case IP_VERSION(8, 11, 0):
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (adev->umc.ras) {
|
|
amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
|
|
|
|
strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
|
|
adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
|
|
adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
|
|
adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
|
|
|
|
/* If don't define special ras_late_init function, use default ras_late_init */
|
|
if (!adev->umc.ras->ras_block.ras_late_init)
|
|
adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
|
|
|
|
/* If not define special ras_cb function, use default ras_cb */
|
|
if (!adev->umc.ras->ras_block.ras_cb)
|
|
adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
|
|
}
|
|
}
|
|
|
|
|
|
static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev)
|
|
{
|
|
switch (adev->ip_versions[MMHUB_HWIP][0]) {
|
|
case IP_VERSION(3, 0, 1):
|
|
adev->mmhub.funcs = &mmhub_v3_0_1_funcs;
|
|
break;
|
|
case IP_VERSION(3, 0, 2):
|
|
adev->mmhub.funcs = &mmhub_v3_0_2_funcs;
|
|
break;
|
|
default:
|
|
adev->mmhub.funcs = &mmhub_v3_0_funcs;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)
|
|
{
|
|
switch (adev->ip_versions[GC_HWIP][0]) {
|
|
case IP_VERSION(11, 0, 3):
|
|
adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs;
|
|
break;
|
|
default:
|
|
adev->gfxhub.funcs = &gfxhub_v3_0_funcs;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int gmc_v11_0_early_init(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
gmc_v11_0_set_gfxhub_funcs(adev);
|
|
gmc_v11_0_set_mmhub_funcs(adev);
|
|
gmc_v11_0_set_gmc_funcs(adev);
|
|
gmc_v11_0_set_irq_funcs(adev);
|
|
gmc_v11_0_set_umc_funcs(adev);
|
|
|
|
adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
|
|
adev->gmc.shared_aperture_end =
|
|
adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
|
|
adev->gmc.private_aperture_start = 0x1000000000000000ULL;
|
|
adev->gmc.private_aperture_end =
|
|
adev->gmc.private_aperture_start + (4ULL << 30) - 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v11_0_late_init(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
int r;
|
|
|
|
r = amdgpu_gmc_allocate_vm_inv_eng(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
r = amdgpu_gmc_ras_late_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
|
|
}
|
|
|
|
static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev,
|
|
struct amdgpu_gmc *mc)
|
|
{
|
|
u64 base = 0;
|
|
|
|
base = adev->mmhub.funcs->get_fb_location(adev);
|
|
|
|
amdgpu_gmc_vram_location(adev, &adev->gmc, base);
|
|
amdgpu_gmc_gart_location(adev, mc);
|
|
amdgpu_gmc_agp_location(adev, mc);
|
|
|
|
/* base offset of vram pages */
|
|
if (amdgpu_sriov_vf(adev))
|
|
adev->vm_manager.vram_base_offset = 0;
|
|
else
|
|
adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);
|
|
}
|
|
|
|
/**
|
|
* gmc_v11_0_mc_init - initialize the memory controller driver params
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
*
|
|
* Look up the amount of vram, vram width, and decide how to place
|
|
* vram and gart within the GPU's physical address space.
|
|
* Returns 0 for success.
|
|
*/
|
|
static int gmc_v11_0_mc_init(struct amdgpu_device *adev)
|
|
{
|
|
int r;
|
|
|
|
/* size in MB on si */
|
|
adev->gmc.mc_vram_size =
|
|
adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
|
|
adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
|
|
|
|
if (!(adev->flags & AMD_IS_APU)) {
|
|
r = amdgpu_device_resize_fb_bar(adev);
|
|
if (r)
|
|
return r;
|
|
}
|
|
adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
|
|
adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
|
|
|
|
#ifdef CONFIG_X86_64
|
|
if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
|
|
adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
|
|
adev->gmc.aper_size = adev->gmc.real_vram_size;
|
|
}
|
|
#endif
|
|
/* In case the PCI BAR is larger than the actual amount of vram */
|
|
adev->gmc.visible_vram_size = adev->gmc.aper_size;
|
|
if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
|
|
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
|
|
|
|
/* set the gart size */
|
|
if (amdgpu_gart_size == -1) {
|
|
adev->gmc.gart_size = 512ULL << 20;
|
|
} else
|
|
adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
|
|
|
|
gmc_v11_0_vram_gtt_location(adev, &adev->gmc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v11_0_gart_init(struct amdgpu_device *adev)
|
|
{
|
|
int r;
|
|
|
|
if (adev->gart.bo) {
|
|
WARN(1, "PCIE GART already initialized\n");
|
|
return 0;
|
|
}
|
|
|
|
/* Initialize common gart structure */
|
|
r = amdgpu_gart_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
adev->gart.table_size = adev->gart.num_gpu_pages * 8;
|
|
adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
|
|
AMDGPU_PTE_EXECUTABLE;
|
|
|
|
return amdgpu_gart_table_vram_alloc(adev);
|
|
}
|
|
|
|
static int gmc_v11_0_sw_init(void *handle)
|
|
{
|
|
int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
adev->mmhub.funcs->init(adev);
|
|
|
|
spin_lock_init(&adev->gmc.invalidate_lock);
|
|
|
|
r = amdgpu_atomfirmware_get_vram_info(adev,
|
|
&vram_width, &vram_type, &vram_vendor);
|
|
adev->gmc.vram_width = vram_width;
|
|
|
|
adev->gmc.vram_type = vram_type;
|
|
adev->gmc.vram_vendor = vram_vendor;
|
|
|
|
switch (adev->ip_versions[GC_HWIP][0]) {
|
|
case IP_VERSION(11, 0, 0):
|
|
case IP_VERSION(11, 0, 1):
|
|
case IP_VERSION(11, 0, 2):
|
|
case IP_VERSION(11, 0, 3):
|
|
case IP_VERSION(11, 0, 4):
|
|
adev->num_vmhubs = 2;
|
|
/*
|
|
* To fulfill 4-level page support,
|
|
* vm size is 256TB (48bit), maximum size,
|
|
* block size 512 (9bit)
|
|
*/
|
|
amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* This interrupt is VMC page fault.*/
|
|
r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC,
|
|
VMC_1_0__SRCID__VM_FAULT,
|
|
&adev->gmc.vm_fault);
|
|
|
|
if (r)
|
|
return r;
|
|
|
|
r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
|
|
UTCL2_1_0__SRCID__FAULT,
|
|
&adev->gmc.vm_fault);
|
|
if (r)
|
|
return r;
|
|
|
|
if (!amdgpu_sriov_vf(adev)) {
|
|
/* interrupt sent to DF. */
|
|
r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,
|
|
&adev->gmc.ecc_irq);
|
|
if (r)
|
|
return r;
|
|
}
|
|
|
|
/*
|
|
* Set the internal MC address mask This is the max address of the GPU's
|
|
* internal address space.
|
|
*/
|
|
adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
|
|
|
|
r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
|
|
if (r) {
|
|
printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
|
|
return r;
|
|
}
|
|
|
|
adev->need_swiotlb = drm_need_swiotlb(44);
|
|
|
|
r = gmc_v11_0_mc_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
amdgpu_gmc_get_vbios_allocations(adev);
|
|
|
|
/* Memory manager */
|
|
r = amdgpu_bo_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
r = gmc_v11_0_gart_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
/*
|
|
* number of VMs
|
|
* VMID 0 is reserved for System
|
|
* amdgpu graphics/compute will use VMIDs 1-7
|
|
* amdkfd will use VMIDs 8-15
|
|
*/
|
|
adev->vm_manager.first_kfd_vmid = 8;
|
|
|
|
amdgpu_vm_manager_init(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* gmc_v11_0_gart_fini - vm fini callback
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
*
|
|
* Tears down the driver GART/VM setup (CIK).
|
|
*/
|
|
static void gmc_v11_0_gart_fini(struct amdgpu_device *adev)
|
|
{
|
|
amdgpu_gart_table_vram_free(adev);
|
|
}
|
|
|
|
static int gmc_v11_0_sw_fini(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
amdgpu_vm_manager_fini(adev);
|
|
gmc_v11_0_gart_fini(adev);
|
|
amdgpu_gem_force_release(adev);
|
|
amdgpu_bo_fini(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev)
|
|
{
|
|
}
|
|
|
|
/**
|
|
* gmc_v11_0_gart_enable - gart enable
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
*/
|
|
static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
|
|
{
|
|
int r;
|
|
bool value;
|
|
|
|
if (adev->gart.bo == NULL) {
|
|
dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
|
|
|
|
r = adev->mmhub.funcs->gart_enable(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
/* Flush HDP after it is initialized */
|
|
adev->hdp.funcs->flush_hdp(adev, NULL);
|
|
|
|
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
|
|
false : true;
|
|
|
|
adev->mmhub.funcs->set_fault_enable_default(adev, value);
|
|
gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
|
|
|
|
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
|
|
(unsigned)(adev->gmc.gart_size >> 20),
|
|
(unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v11_0_hw_init(void *handle)
|
|
{
|
|
int r;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
/* The sequence of these two function calls matters.*/
|
|
gmc_v11_0_init_golden_registers(adev);
|
|
|
|
r = gmc_v11_0_gart_enable(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
if (adev->umc.funcs && adev->umc.funcs->init_registers)
|
|
adev->umc.funcs->init_registers(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* gmc_v11_0_gart_disable - gart disable
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
*
|
|
* This disables all VM page table.
|
|
*/
|
|
static void gmc_v11_0_gart_disable(struct amdgpu_device *adev)
|
|
{
|
|
adev->mmhub.funcs->gart_disable(adev);
|
|
}
|
|
|
|
static int gmc_v11_0_hw_fini(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
if (amdgpu_sriov_vf(adev)) {
|
|
/* full access mode, so don't touch any GMC register */
|
|
DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
|
|
return 0;
|
|
}
|
|
|
|
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
|
|
gmc_v11_0_gart_disable(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v11_0_suspend(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
gmc_v11_0_hw_fini(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v11_0_resume(void *handle)
|
|
{
|
|
int r;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
r = gmc_v11_0_hw_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
amdgpu_vmid_reset_all(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool gmc_v11_0_is_idle(void *handle)
|
|
{
|
|
/* MC is always ready in GMC v11.*/
|
|
return true;
|
|
}
|
|
|
|
static int gmc_v11_0_wait_for_idle(void *handle)
|
|
{
|
|
/* There is no need to wait for MC idle in GMC v11.*/
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v11_0_soft_reset(void *handle)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v11_0_set_clockgating_state(void *handle,
|
|
enum amd_clockgating_state state)
|
|
{
|
|
int r;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
r = adev->mmhub.funcs->set_clockgating(adev, state);
|
|
if (r)
|
|
return r;
|
|
|
|
return athub_v3_0_set_clockgating(adev, state);
|
|
}
|
|
|
|
static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
adev->mmhub.funcs->get_clockgating(adev, flags);
|
|
|
|
athub_v3_0_get_clockgating(adev, flags);
|
|
}
|
|
|
|
static int gmc_v11_0_set_powergating_state(void *handle,
|
|
enum amd_powergating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
const struct amd_ip_funcs gmc_v11_0_ip_funcs = {
|
|
.name = "gmc_v11_0",
|
|
.early_init = gmc_v11_0_early_init,
|
|
.sw_init = gmc_v11_0_sw_init,
|
|
.hw_init = gmc_v11_0_hw_init,
|
|
.late_init = gmc_v11_0_late_init,
|
|
.sw_fini = gmc_v11_0_sw_fini,
|
|
.hw_fini = gmc_v11_0_hw_fini,
|
|
.suspend = gmc_v11_0_suspend,
|
|
.resume = gmc_v11_0_resume,
|
|
.is_idle = gmc_v11_0_is_idle,
|
|
.wait_for_idle = gmc_v11_0_wait_for_idle,
|
|
.soft_reset = gmc_v11_0_soft_reset,
|
|
.set_clockgating_state = gmc_v11_0_set_clockgating_state,
|
|
.set_powergating_state = gmc_v11_0_set_powergating_state,
|
|
.get_clockgating_state = gmc_v11_0_get_clockgating_state,
|
|
};
|
|
|
|
const struct amdgpu_ip_block_version gmc_v11_0_ip_block = {
|
|
.type = AMD_IP_BLOCK_TYPE_GMC,
|
|
.major = 11,
|
|
.minor = 0,
|
|
.rev = 0,
|
|
.funcs = &gmc_v11_0_ip_funcs,
|
|
};
|