596 lines
18 KiB
C
596 lines
18 KiB
C
/*
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* Copyright 2012-14 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DC_STREAM_H_
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#define DC_STREAM_H_
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#include "dc_types.h"
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#include "grph_object_defs.h"
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/*******************************************************************************
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* Stream Interfaces
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******************************************************************************/
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struct timing_sync_info {
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int group_id;
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int group_size;
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bool master;
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};
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struct dc_stream_status {
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int primary_otg_inst;
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int stream_enc_inst;
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/**
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* @plane_count: Total of planes attached to a single stream
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*/
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int plane_count;
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int audio_inst;
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struct timing_sync_info timing_sync_info;
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struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
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bool is_abm_supported;
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};
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enum hubp_dmdata_mode {
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DMDATA_SW_MODE,
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DMDATA_HW_MODE
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};
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struct dc_dmdata_attributes {
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/* Specifies whether dynamic meta data will be updated by software
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* or has to be fetched by hardware (DMA mode)
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*/
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enum hubp_dmdata_mode dmdata_mode;
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/* Specifies if current dynamic meta data is to be used only for the current frame */
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bool dmdata_repeat;
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/* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */
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uint32_t dmdata_size;
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/* Specifies if a new dynamic meta data should be fetched for an upcoming frame */
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bool dmdata_updated;
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/* If hardware mode is used, the base address where DMDATA surface is located */
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PHYSICAL_ADDRESS_LOC address;
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/* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */
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bool dmdata_qos_mode;
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/* If qos_mode = 1, this is the QOS value to be used: */
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uint32_t dmdata_qos_level;
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/* Specifies the value in unit of REFCLK cycles to be added to the
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* current time to produce the Amortized deadline for Dynamic Metadata chunk request
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*/
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uint32_t dmdata_dl_delta;
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/* An unbounded array of uint32s, represents software dmdata to be loaded */
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uint32_t *dmdata_sw_data;
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};
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struct dc_writeback_info {
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bool wb_enabled;
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int dwb_pipe_inst;
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struct dc_dwb_params dwb_params;
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struct mcif_buf_params mcif_buf_params;
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struct mcif_warmup_params mcif_warmup_params;
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/* the plane that is the input to TOP_MUX for MPCC that is the DWB source */
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struct dc_plane_state *writeback_source_plane;
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/* source MPCC instance. for use by internally by dc */
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int mpcc_inst;
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};
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struct dc_writeback_update {
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unsigned int num_wb_info;
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struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
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};
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enum vertical_interrupt_ref_point {
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START_V_UPDATE = 0,
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START_V_SYNC,
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INVALID_POINT
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//For now, only v_update interrupt is used.
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//START_V_BLANK,
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//START_V_ACTIVE
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};
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struct periodic_interrupt_config {
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enum vertical_interrupt_ref_point ref_point;
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int lines_offset;
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};
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struct dc_mst_stream_bw_update {
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bool is_increase; // is bandwidth reduced or increased
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uint32_t mst_stream_bw; // new mst bandwidth in kbps
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};
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union stream_update_flags {
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struct {
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uint32_t scaling:1;
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uint32_t out_tf:1;
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uint32_t out_csc:1;
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uint32_t abm_level:1;
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uint32_t dpms_off:1;
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uint32_t gamut_remap:1;
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uint32_t wb_update:1;
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uint32_t dsc_changed : 1;
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uint32_t mst_bw : 1;
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uint32_t crtc_timing_adjust : 1;
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} bits;
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uint32_t raw;
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};
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struct test_pattern {
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enum dp_test_pattern type;
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enum dp_test_pattern_color_space color_space;
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struct link_training_settings const *p_link_settings;
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unsigned char const *p_custom_pattern;
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unsigned int cust_pattern_size;
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};
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#define SUBVP_DRR_MARGIN_US 600 // 600us for DRR margin (SubVP + DRR)
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enum mall_stream_type {
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SUBVP_NONE, // subvp not in use
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SUBVP_MAIN, // subvp in use, this stream is main stream
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SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream
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};
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struct mall_stream_config {
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/* MALL stream config to indicate if the stream is phantom or not.
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* We will use a phantom stream to indicate that the pipe is phantom.
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*/
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enum mall_stream_type type;
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struct dc_stream_state *paired_stream; // master / slave stream
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};
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/* Temp struct used to save and restore MALL config
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* during validation.
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*
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* TODO: Move MALL config into dc_state instead of stream struct
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* to avoid needing to save/restore.
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*/
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struct mall_temp_config {
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struct mall_stream_config mall_stream_config[MAX_PIPES];
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bool is_phantom_plane[MAX_PIPES];
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};
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struct dc_stream_state {
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// sink is deprecated, new code should not reference
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// this pointer
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struct dc_sink *sink;
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struct dc_link *link;
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/* For dynamic link encoder assignment, update the link encoder assigned to
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* a stream via the volatile dc_state rather than the static dc_link.
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*/
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struct link_encoder *link_enc;
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struct dc_panel_patch sink_patches;
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union display_content_support content_support;
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struct dc_crtc_timing timing;
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struct dc_crtc_timing_adjust adjust;
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struct dc_info_packet vrr_infopacket;
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struct dc_info_packet vsc_infopacket;
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struct dc_info_packet vsp_infopacket;
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struct dc_info_packet hfvsif_infopacket;
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struct dc_info_packet vtem_infopacket;
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struct dc_info_packet adaptive_sync_infopacket;
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uint8_t dsc_packed_pps[128];
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struct rect src; /* composition area */
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struct rect dst; /* stream addressable area */
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struct audio_info audio_info;
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struct dc_info_packet hdr_static_metadata;
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PHYSICAL_ADDRESS_LOC dmdata_address;
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bool use_dynamic_meta;
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struct dc_transfer_func *out_transfer_func;
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struct colorspace_transform gamut_remap_matrix;
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struct dc_csc_transform csc_color_matrix;
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enum dc_color_space output_color_space;
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enum dc_dither_option dither_option;
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enum view_3d_format view_format;
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bool use_vsc_sdp_for_colorimetry;
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bool ignore_msa_timing_param;
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/**
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* @allow_freesync:
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*
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* It say if Freesync is enabled or not.
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*/
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bool allow_freesync;
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/**
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* @vrr_active_variable:
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*
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* It describes if VRR is in use.
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*/
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bool vrr_active_variable;
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bool freesync_on_desktop;
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bool converter_disable_audio;
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uint8_t qs_bit;
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uint8_t qy_bit;
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/* TODO: custom INFO packets */
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/* TODO: ABM info (DMCU) */
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/* TODO: CEA VIC */
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/* DMCU info */
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unsigned int abm_level;
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struct periodic_interrupt_config periodic_interrupt;
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/* from core_stream struct */
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struct dc_context *ctx;
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/* used by DCP and FMT */
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struct bit_depth_reduction_params bit_depth_params;
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struct clamping_and_pixel_encoding_params clamping;
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int phy_pix_clk;
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enum signal_type signal;
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bool dpms_off;
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void *dm_stream_context;
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struct dc_cursor_attributes cursor_attributes;
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struct dc_cursor_position cursor_position;
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uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
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/* from stream struct */
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struct kref refcount;
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struct crtc_trigger_info triggered_crtc_reset;
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/* writeback */
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unsigned int num_wb_info;
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struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
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const struct dc_transfer_func *func_shaper;
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const struct dc_3dlut *lut3d_func;
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/* Computed state bits */
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bool mode_changed : 1;
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/* Output from DC when stream state is committed or altered
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* DC may only access these values during:
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* dc_commit_state, dc_commit_state_no_check, dc_commit_streams
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* values may not change outside of those calls
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*/
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struct {
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// For interrupt management, some hardware instance
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// offsets need to be exposed to DM
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uint8_t otg_offset;
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} out;
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bool apply_edp_fast_boot_optimization;
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bool apply_seamless_boot_optimization;
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uint32_t apply_boot_odm_mode;
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uint32_t stream_id;
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struct test_pattern test_pattern;
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union stream_update_flags update_flags;
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bool has_non_synchronizable_pclk;
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bool vblank_synchronized;
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struct mall_stream_config mall_stream_config;
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};
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#define ABM_LEVEL_IMMEDIATE_DISABLE 255
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struct dc_stream_update {
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struct dc_stream_state *stream;
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struct rect src;
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struct rect dst;
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struct dc_transfer_func *out_transfer_func;
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struct dc_info_packet *hdr_static_metadata;
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unsigned int *abm_level;
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struct periodic_interrupt_config *periodic_interrupt;
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struct dc_info_packet *vrr_infopacket;
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struct dc_info_packet *vsc_infopacket;
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struct dc_info_packet *vsp_infopacket;
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struct dc_info_packet *hfvsif_infopacket;
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struct dc_info_packet *vtem_infopacket;
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struct dc_info_packet *adaptive_sync_infopacket;
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bool *dpms_off;
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bool integer_scaling_update;
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bool *allow_freesync;
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bool *vrr_active_variable;
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struct colorspace_transform *gamut_remap;
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enum dc_color_space *output_color_space;
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enum dc_dither_option *dither_option;
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struct dc_csc_transform *output_csc_transform;
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struct dc_writeback_update *wb_update;
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struct dc_dsc_config *dsc_config;
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struct dc_mst_stream_bw_update *mst_bw_update;
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struct dc_transfer_func *func_shaper;
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struct dc_3dlut *lut3d_func;
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struct test_pattern *pending_test_pattern;
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struct dc_crtc_timing_adjust *crtc_timing_adjust;
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};
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bool dc_is_stream_unchanged(
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struct dc_stream_state *old_stream, struct dc_stream_state *stream);
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bool dc_is_stream_scaling_unchanged(
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struct dc_stream_state *old_stream, struct dc_stream_state *stream);
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/*
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* Setup stream attributes if no stream updates are provided
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* there will be no impact on the stream parameters
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*
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* Set up surface attributes and associate to a stream
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* The surfaces parameter is an absolute set of all surface active for the stream.
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* If no surfaces are provided, the stream will be blanked; no memory read.
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* Any flip related attribute changes must be done through this interface.
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*
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* After this call:
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* Surfaces attributes are programmed and configured to be composed into stream.
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* This does not trigger a flip. No surface address is programmed.
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*
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*/
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bool dc_update_planes_and_stream(struct dc *dc,
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struct dc_surface_update *surface_updates, int surface_count,
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struct dc_stream_state *dc_stream,
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struct dc_stream_update *stream_update);
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/*
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* Set up surface attributes and associate to a stream
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* The surfaces parameter is an absolute set of all surface active for the stream.
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* If no surfaces are provided, the stream will be blanked; no memory read.
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* Any flip related attribute changes must be done through this interface.
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*
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* After this call:
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* Surfaces attributes are programmed and configured to be composed into stream.
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* This does not trigger a flip. No surface address is programmed.
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*/
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void dc_commit_updates_for_stream(struct dc *dc,
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struct dc_surface_update *srf_updates,
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int surface_count,
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struct dc_stream_state *stream,
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struct dc_stream_update *stream_update,
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struct dc_state *state);
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/*
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* Log the current stream state.
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*/
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void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
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uint8_t dc_get_current_stream_count(struct dc *dc);
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struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
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/*
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* Return the current frame counter.
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*/
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uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
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/*
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* Send dp sdp message.
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*/
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bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
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const uint8_t *custom_sdp_message,
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unsigned int sdp_message_size);
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/* TODO: Return parsed values rather than direct register read
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* This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos)
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* being refactored properly to be dce-specific
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*/
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bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
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uint32_t *v_blank_start,
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uint32_t *v_blank_end,
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uint32_t *h_position,
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uint32_t *v_position);
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enum dc_status dc_add_stream_to_ctx(
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struct dc *dc,
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struct dc_state *new_ctx,
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struct dc_stream_state *stream);
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enum dc_status dc_remove_stream_from_ctx(
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struct dc *dc,
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struct dc_state *new_ctx,
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struct dc_stream_state *stream);
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bool dc_add_plane_to_context(
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const struct dc *dc,
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struct dc_stream_state *stream,
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struct dc_plane_state *plane_state,
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struct dc_state *context);
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bool dc_remove_plane_from_context(
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const struct dc *dc,
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struct dc_stream_state *stream,
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struct dc_plane_state *plane_state,
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struct dc_state *context);
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bool dc_rem_all_planes_for_stream(
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const struct dc *dc,
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struct dc_stream_state *stream,
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struct dc_state *context);
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bool dc_add_all_planes_for_stream(
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const struct dc *dc,
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struct dc_stream_state *stream,
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struct dc_plane_state * const *plane_states,
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int plane_count,
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struct dc_state *context);
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bool dc_stream_add_writeback(struct dc *dc,
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struct dc_stream_state *stream,
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struct dc_writeback_info *wb_info);
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bool dc_stream_remove_writeback(struct dc *dc,
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struct dc_stream_state *stream,
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uint32_t dwb_pipe_inst);
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enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
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struct dc_state *state,
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struct dc_stream_state *stream);
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bool dc_stream_warmup_writeback(struct dc *dc,
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int num_dwb,
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struct dc_writeback_info *wb_info);
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bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);
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bool dc_stream_set_dynamic_metadata(struct dc *dc,
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struct dc_stream_state *stream,
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struct dc_dmdata_attributes *dmdata_attr);
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enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
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/*
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* Set up streams and links associated to drive sinks
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* The streams parameter is an absolute set of all active streams.
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*
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* After this call:
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* Phy, Encoder, Timing Generator are programmed and enabled.
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* New streams are enabled with blank stream; no memory read.
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*/
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/*
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* Enable stereo when commit_streams is not required,
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* for example, frame alternate.
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*/
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void dc_enable_stereo(
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struct dc *dc,
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struct dc_state *context,
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struct dc_stream_state *streams[],
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uint8_t stream_count);
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/* Triggers multi-stream synchronization. */
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void dc_trigger_sync(struct dc *dc, struct dc_state *context);
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enum surface_update_type dc_check_update_surfaces_for_stream(
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struct dc *dc,
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struct dc_surface_update *updates,
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int surface_count,
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struct dc_stream_update *stream_update,
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const struct dc_stream_status *stream_status);
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/**
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* Create a new default stream for the requested sink
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*/
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struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
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struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream);
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void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink);
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void dc_stream_retain(struct dc_stream_state *dc_stream);
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void dc_stream_release(struct dc_stream_state *dc_stream);
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struct dc_stream_status *dc_stream_get_status_from_state(
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struct dc_state *state,
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struct dc_stream_state *stream);
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struct dc_stream_status *dc_stream_get_status(
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struct dc_stream_state *dc_stream);
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#ifndef TRIM_FSFT
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bool dc_optimize_timing_for_fsft(
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struct dc_stream_state *pStream,
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unsigned int max_input_rate_in_khz);
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#endif
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/*******************************************************************************
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* Cursor interfaces - To manages the cursor within a stream
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******************************************************************************/
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/* TODO: Deprecated once we switch to dc_set_cursor_position */
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bool dc_stream_set_cursor_attributes(
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struct dc_stream_state *stream,
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const struct dc_cursor_attributes *attributes);
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bool dc_stream_set_cursor_position(
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struct dc_stream_state *stream,
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const struct dc_cursor_position *position);
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bool dc_stream_adjust_vmin_vmax(struct dc *dc,
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struct dc_stream_state *stream,
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struct dc_crtc_timing_adjust *adjust);
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bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
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struct dc_stream_state *stream,
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uint32_t *refresh_rate);
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bool dc_stream_get_crtc_position(struct dc *dc,
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struct dc_stream_state **stream,
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int num_streams,
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unsigned int *v_pos,
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unsigned int *nom_v_pos);
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#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
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bool dc_stream_forward_crc_window(struct dc_stream_state *stream,
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struct rect *rect,
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bool is_stop);
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#endif
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bool dc_stream_configure_crc(struct dc *dc,
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struct dc_stream_state *stream,
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struct crc_params *crc_window,
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bool enable,
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bool continuous);
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bool dc_stream_get_crc(struct dc *dc,
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struct dc_stream_state *stream,
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uint32_t *r_cr,
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uint32_t *g_y,
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uint32_t *b_cb);
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void dc_stream_set_static_screen_params(struct dc *dc,
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struct dc_stream_state **stream,
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int num_streams,
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const struct dc_static_screen_params *params);
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void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
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enum dc_dynamic_expansion option);
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void dc_stream_set_dither_option(struct dc_stream_state *stream,
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enum dc_dither_option option);
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bool dc_stream_set_gamut_remap(struct dc *dc,
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const struct dc_stream_state *stream);
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bool dc_stream_program_csc_matrix(struct dc *dc,
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struct dc_stream_state *stream);
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bool dc_stream_get_crtc_position(struct dc *dc,
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struct dc_stream_state **stream,
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int num_streams,
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unsigned int *v_pos,
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unsigned int *nom_v_pos);
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struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream);
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void dc_dmub_update_dirty_rect(struct dc *dc,
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int surface_count,
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struct dc_stream_state *stream,
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struct dc_surface_update *srf_updates,
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struct dc_state *context);
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#endif /* DC_STREAM_H_ */
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