205 lines
5.8 KiB
C
205 lines
5.8 KiB
C
/* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_MPCC_DCN10_H__
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#define __DC_MPCC_DCN10_H__
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#include "mpc.h"
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#define TO_DCN10_MPC(mpc_base) \
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container_of(mpc_base, struct dcn10_mpc, base)
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#define MPC_COMMON_REG_LIST_DCN1_0(inst) \
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SRII(MPCC_TOP_SEL, MPCC, inst),\
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SRII(MPCC_BOT_SEL, MPCC, inst),\
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SRII(MPCC_CONTROL, MPCC, inst),\
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SRII(MPCC_STATUS, MPCC, inst),\
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SRII(MPCC_OPP_ID, MPCC, inst),\
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SRII(MPCC_BG_G_Y, MPCC, inst),\
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SRII(MPCC_BG_R_CR, MPCC, inst),\
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SRII(MPCC_BG_B_CB, MPCC, inst),\
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SRII(MPCC_SM_CONTROL, MPCC, inst),\
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SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
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#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \
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SRII(MUX, MPC_OUT, inst),\
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VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)
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#define MPC_COMMON_REG_VARIABLE_LIST \
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uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
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uint32_t MPCC_BOT_SEL[MAX_MPCC]; \
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uint32_t MPCC_CONTROL[MAX_MPCC]; \
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uint32_t MPCC_STATUS[MAX_MPCC]; \
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uint32_t MPCC_OPP_ID[MAX_MPCC]; \
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uint32_t MPCC_BG_G_Y[MAX_MPCC]; \
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uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
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uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
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uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
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uint32_t MUX[MAX_OPP]; \
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uint32_t MPCC_UPDATE_LOCK_SEL[MAX_MPCC]; \
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uint32_t CUR[MAX_OPP];
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#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
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SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
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SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
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SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
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SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
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SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
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SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
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SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
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SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
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SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
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SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
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SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
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SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
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SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
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SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
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SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\
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SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\
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SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\
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SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\
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SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\
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SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\
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SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
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SF(MPCC0_MPCC_UPDATE_LOCK_SEL, MPCC_UPDATE_LOCK_SEL, mask_sh)
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#define MPC_REG_FIELD_LIST(type) \
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type MPCC_TOP_SEL;\
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type MPCC_BOT_SEL;\
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type MPCC_MODE;\
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type MPCC_ALPHA_BLND_MODE;\
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type MPCC_ALPHA_MULTIPLIED_MODE;\
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type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\
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type MPCC_GLOBAL_ALPHA;\
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type MPCC_GLOBAL_GAIN;\
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type MPCC_IDLE;\
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type MPCC_BUSY;\
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type MPCC_OPP_ID;\
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type MPCC_BG_G_Y;\
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type MPCC_BG_R_CR;\
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type MPCC_BG_B_CB;\
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type MPCC_SM_EN;\
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type MPCC_SM_MODE;\
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type MPCC_SM_FRAME_ALT;\
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type MPCC_SM_FIELD_ALT;\
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type MPCC_SM_FORCE_NEXT_FRAME_POL;\
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type MPCC_SM_FORCE_NEXT_TOP_POL;\
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type MPC_OUT_MUX;\
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type MPCC_UPDATE_LOCK_SEL;\
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type CUR_VUPDATE_LOCK_SET;
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struct dcn_mpc_registers {
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MPC_COMMON_REG_VARIABLE_LIST
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};
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struct dcn_mpc_shift {
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MPC_REG_FIELD_LIST(uint8_t)
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};
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struct dcn_mpc_mask {
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MPC_REG_FIELD_LIST(uint32_t)
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};
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struct dcn10_mpc {
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struct mpc base;
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int mpcc_in_use_mask;
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int num_mpcc;
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const struct dcn_mpc_registers *mpc_regs;
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const struct dcn_mpc_shift *mpc_shift;
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const struct dcn_mpc_mask *mpc_mask;
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};
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void dcn10_mpc_construct(struct dcn10_mpc *mpcc10,
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struct dc_context *ctx,
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const struct dcn_mpc_registers *mpc_regs,
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const struct dcn_mpc_shift *mpc_shift,
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const struct dcn_mpc_mask *mpc_mask,
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int num_mpcc);
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struct mpcc *mpc1_insert_plane(
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struct mpc *mpc,
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struct mpc_tree *tree,
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struct mpcc_blnd_cfg *blnd_cfg,
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struct mpcc_sm_cfg *sm_cfg,
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struct mpcc *insert_above_mpcc,
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int dpp_id,
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int mpcc_id);
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void mpc1_remove_mpcc(
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struct mpc *mpc,
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struct mpc_tree *tree,
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struct mpcc *mpcc);
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void mpc1_mpc_init(
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struct mpc *mpc);
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void mpc1_mpc_init_single_inst(
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struct mpc *mpc,
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unsigned int mpcc_id);
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void mpc1_assert_idle_mpcc(
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struct mpc *mpc,
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int id);
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void mpc1_set_bg_color(
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struct mpc *mpc,
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struct tg_color *bg_color,
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int id);
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void mpc1_update_stereo_mix(
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struct mpc *mpc,
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struct mpcc_sm_cfg *sm_cfg,
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int mpcc_id);
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bool mpc1_is_mpcc_idle(
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struct mpc *mpc,
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int mpcc_id);
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void mpc1_assert_mpcc_idle_before_connect(
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struct mpc *mpc,
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int mpcc_id);
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void mpc1_init_mpcc_list_from_hw(
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struct mpc *mpc,
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struct mpc_tree *tree);
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struct mpcc *mpc1_get_mpcc(
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struct mpc *mpc,
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int mpcc_id);
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struct mpcc *mpc1_get_mpcc_for_dpp(
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struct mpc_tree *tree,
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int dpp_id);
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void mpc1_read_mpcc_state(
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struct mpc *mpc,
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int mpcc_inst,
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struct mpcc_state *s);
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void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
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unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);
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#endif
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