432 lines
17 KiB
C
432 lines
17 KiB
C
/* Copyright 2012-17 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_DWBC_DCN20_H__
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#define __DC_DWBC_DCN20_H__
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#define TO_DCN20_DWBC(dwbc_base) \
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container_of(dwbc_base, struct dcn20_dwbc, base)
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#define DWBC_COMMON_REG_LIST_DCN2_0(inst) \
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SRI2_DWB(WB_ENABLE, CNV, inst),\
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SRI2_DWB(WB_EC_CONFIG, CNV, inst),\
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SRI2_DWB(CNV_MODE, CNV, inst),\
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SRI2_DWB(CNV_WINDOW_START, CNV, inst),\
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SRI2_DWB(CNV_WINDOW_SIZE, CNV, inst),\
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SRI2_DWB(CNV_UPDATE, CNV, inst),\
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SRI2_DWB(CNV_SOURCE_SIZE, CNV, inst),\
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SRI2_DWB(CNV_TEST_CNTL, CNV, inst),\
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SRI2_DWB(CNV_TEST_CRC_RED, CNV, inst),\
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SRI2_DWB(CNV_TEST_CRC_GREEN, CNV, inst),\
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SRI2_DWB(CNV_TEST_CRC_BLUE, CNV, inst),\
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SRI2_DWB(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\
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SRI2_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\
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SRI2_DWB(WBSCL_MODE, WBSCL, inst),\
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SRI2_DWB(WBSCL_TAP_CONTROL, WBSCL, inst),\
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SRI2_DWB(WBSCL_DEST_SIZE, WBSCL, inst),\
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SRI2_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\
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SRI2_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\
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SRI2_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\
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SRI2_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\
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SRI2_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\
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SRI2_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\
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SRI2_DWB(WBSCL_ROUND_OFFSET, WBSCL, inst),\
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SRI2_DWB(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\
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SRI2_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\
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SRI2_DWB(WBSCL_TEST_CNTL, WBSCL, inst),\
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SRI2_DWB(WBSCL_TEST_CRC_RED, WBSCL, inst),\
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SRI2_DWB(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\
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SRI2_DWB(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\
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SRI2_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\
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SRI2_DWB(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\
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SRI2_DWB(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\
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SRI2_DWB(WBSCL_CLAMP_CBCR, WBSCL, inst),\
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SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\
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SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\
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SRI2_DWB(WBSCL_DEBUG, WBSCL, inst),\
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SRI2_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\
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SRI2_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\
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SRI2_DWB(WB_DEBUG_CTRL, CNV, inst),\
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SRI2_DWB(WB_DBG_MODE, CNV, inst),\
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SRI2_DWB(WB_HW_DEBUG, CNV, inst),\
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SRI2_DWB(CNV_TEST_DEBUG_INDEX, CNV, inst),\
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SRI2_DWB(CNV_TEST_DEBUG_DATA, CNV, inst),\
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SRI2_DWB(WB_SOFT_RESET, CNV, inst),\
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SRI2_DWB(WB_WARM_UP_MODE_CTL1, CNV, inst),\
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SRI2_DWB(WB_WARM_UP_MODE_CTL2, CNV, inst)
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#define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
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SF_DWB(WB_ENABLE, WB_ENABLE, mask_sh),\
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SF_DWB(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
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SF_DWB(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
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SF_DWB(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
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SF_DWB(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
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SF_DWB(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
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SF_DWB(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
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SF_DWB(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
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SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
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SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\
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SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\
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SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\
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SF_DWB(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\
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SF_DWB(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\
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SF_DWB(CNV_MODE, CNV_OUT_BPC, mask_sh),\
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SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\
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SF_DWB(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
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SF_DWB(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
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SF_DWB(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
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SF_DWB(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
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SF_DWB(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
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SF_DWB(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
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SF_DWB(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
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SF_DWB(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
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SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\
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SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
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SF_DWB(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\
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SF_DWB(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\
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SF_DWB(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\
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SF_DWB(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\
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SF_DWB(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\
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SF_DWB(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\
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SF_DWB(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\
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SF_DWB(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\
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SF_DWB(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\
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SF_DWB(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\
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SF_DWB(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\
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SF_DWB(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\
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SF_DWB(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\
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SF_DWB(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\
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SF_DWB(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\
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SF_DWB(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\
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SF_DWB(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\
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SF_DWB(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\
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SF_DWB(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\
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SF_DWB(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\
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SF_DWB(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\
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SF_DWB(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\
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SF_DWB(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
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SF_DWB(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\
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SF_DWB(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\
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SF_DWB(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
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SF_DWB(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
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SF_DWB(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\
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SF_DWB(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\
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SF_DWB(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
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SF_DWB(WBSCL_MODE, WBSCL_MODE, mask_sh),\
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SF_DWB(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\
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SF_DWB(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\
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SF_DWB(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\
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SF_DWB(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\
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SF_DWB(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\
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SF_DWB(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\
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SF_DWB(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\
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SF_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\
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SF_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\
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SF_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\
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SF_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\
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SF_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\
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SF_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\
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SF_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\
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SF_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\
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SF_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\
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SF_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\
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SF_DWB(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\
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SF_DWB(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\
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SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\
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SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\
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SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\
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SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\
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SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\
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SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\
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SF_DWB(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\
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SF_DWB(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\
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SF_DWB(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\
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SF_DWB(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\
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SF_DWB(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\
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SF_DWB(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\
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SF_DWB(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\
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SF_DWB(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\
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SF_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\
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SF_DWB(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\
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SF_DWB(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\
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SF_DWB(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\
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SF_DWB(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\
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SF_DWB(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\
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SF_DWB(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\
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SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\
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SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\
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SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\
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SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\
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SF_DWB(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\
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SF_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\
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SF_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\
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SF_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\
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SF_DWB(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\
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SF_DWB(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\
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SF_DWB(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\
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SF_DWB(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\
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SF_DWB(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\
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SF_DWB(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh)
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#define DWBC_REG_FIELD_LIST_DCN2_0(type) \
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type WB_ENABLE;\
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type DISPCLK_R_WB_GATE_DIS;\
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type DISPCLK_G_WB_GATE_DIS;\
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type DISPCLK_G_WBSCL_GATE_DIS;\
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type WB_TEST_CLK_SEL;\
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type WB_LB_LS_DIS;\
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type WB_LB_SD_DIS;\
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type WB_LUT_LS_DIS;\
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type WBSCL_LB_MEM_PWR_MODE_SEL;\
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type WBSCL_LB_MEM_PWR_DIS;\
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type WBSCL_LB_MEM_PWR_FORCE;\
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type WBSCL_LB_MEM_PWR_STATE;\
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type WB_RAM_PW_SAVE_MODE;\
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type WBSCL_LUT_MEM_PWR_STATE;\
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type CNV_OUT_BPC;\
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type CNV_FRAME_CAPTURE_RATE;\
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type CNV_WINDOW_CROP_EN;\
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type CNV_STEREO_TYPE;\
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type CNV_INTERLACED_MODE;\
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type CNV_EYE_SELECTION;\
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type CNV_STEREO_POLARITY;\
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type CNV_INTERLACED_FIELD_ORDER;\
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type CNV_STEREO_SPLIT;\
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type CNV_NEW_CONTENT;\
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type CNV_FRAME_CAPTURE_EN_CURRENT;\
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type CNV_FRAME_CAPTURE_EN;\
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type CNV_WINDOW_START_X;\
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type CNV_WINDOW_START_Y;\
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type CNV_WINDOW_WIDTH;\
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type CNV_WINDOW_HEIGHT;\
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type CNV_UPDATE_PENDING;\
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type CNV_UPDATE_TAKEN;\
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type CNV_UPDATE_LOCK;\
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type CNV_SOURCE_WIDTH;\
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type CNV_SOURCE_HEIGHT;\
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type CNV_TEST_CRC_EN;\
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type CNV_TEST_CRC_CONT_EN;\
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type CNV_TEST_CRC_RED_MASK;\
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type CNV_TEST_CRC_SIG_RED;\
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type CNV_TEST_CRC_GREEN_MASK;\
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type CNV_TEST_CRC_SIG_GREEN;\
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type CNV_TEST_CRC_BLUE_MASK;\
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type CNV_TEST_CRC_SIG_BLUE;\
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type WB_DEBUG_EN;\
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type WB_DEBUG_SEL;\
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type WB_DBG_MODE_EN;\
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type WB_DBG_DIN_FMT;\
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type WB_DBG_36MODE;\
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type WB_DBG_CMAP;\
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type WB_DBG_PXLRATE_ERROR;\
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type WB_DBG_SOURCE_WIDTH;\
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type WB_HW_DEBUG;\
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type CNV_TEST_DEBUG_INDEX;\
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type CNV_TEST_DEBUG_WRITE_EN;\
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type CNV_TEST_DEBUG_DATA;\
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type WB_SOFT_RESET;\
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type WBSCL_COEF_RAM_TAP_PAIR_IDX;\
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type WBSCL_COEF_RAM_PHASE;\
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type WBSCL_COEF_RAM_FILTER_TYPE;\
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type WBSCL_COEF_RAM_SEL;\
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type WBSCL_COEF_RAM_SEL_CURRENT;\
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type WBSCL_COEF_RAM_RD_SEL;\
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type WBSCL_COEF_RAM_EVEN_TAP_COEF;\
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type WBSCL_COEF_RAM_EVEN_TAP_COEF_EN;\
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type WBSCL_COEF_RAM_ODD_TAP_COEF;\
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type WBSCL_COEF_RAM_ODD_TAP_COEF_EN;\
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type WBSCL_MODE;\
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type WBSCL_OUT_BIT_DEPTH;\
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type WBSCL_V_NUM_OF_TAPS_Y_RGB;\
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type WBSCL_V_NUM_OF_TAPS_CBCR;\
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type WBSCL_H_NUM_OF_TAPS_Y_RGB;\
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type WBSCL_H_NUM_OF_TAPS_CBCR;\
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type WBSCL_DEST_HEIGHT;\
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type WBSCL_DEST_WIDTH;\
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type WBSCL_H_SCALE_RATIO;\
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type WBSCL_H_INIT_FRAC_Y_RGB;\
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type WBSCL_H_INIT_INT_Y_RGB;\
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type WBSCL_H_INIT_FRAC_CBCR;\
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type WBSCL_H_INIT_INT_CBCR;\
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type WBSCL_V_SCALE_RATIO;\
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type WBSCL_V_INIT_FRAC_Y_RGB;\
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type WBSCL_V_INIT_INT_Y_RGB;\
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type WBSCL_V_INIT_FRAC_CBCR;\
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type WBSCL_V_INIT_INT_CBCR;\
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type WBSCL_ROUND_OFFSET_Y_RGB;\
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type WBSCL_ROUND_OFFSET_CBCR;\
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type WBSCL_DATA_OVERFLOW_FLAG;\
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type WBSCL_DATA_OVERFLOW_ACK;\
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type WBSCL_DATA_OVERFLOW_MASK;\
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type WBSCL_DATA_OVERFLOW_INT_STATUS;\
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type WBSCL_DATA_OVERFLOW_INT_TYPE;\
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type WBSCL_HOST_CONFLICT_FLAG;\
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type WBSCL_HOST_CONFLICT_ACK;\
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type WBSCL_HOST_CONFLICT_MASK;\
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type WBSCL_HOST_CONFLICT_INT_STATUS;\
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type WBSCL_HOST_CONFLICT_INT_TYPE;\
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type WBSCL_TEST_CRC_EN;\
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type WBSCL_TEST_CRC_CONT_EN;\
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type WBSCL_TEST_CRC_RED_MASK;\
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type WBSCL_TEST_CRC_SIG_RED;\
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type WBSCL_TEST_CRC_GREEN_MASK;\
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type WBSCL_TEST_CRC_SIG_GREEN;\
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type WBSCL_TEST_CRC_BLUE_MASK;\
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type WBSCL_TEST_CRC_SIG_BLUE;\
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type WBSCL_BACKPRESSURE_CNT_EN;\
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type WB_MCIF_Y_MAX_BACKPRESSURE;\
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type WB_MCIF_C_MAX_BACKPRESSURE;\
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type WBSCL_CLAMP_UPPER_Y_RGB;\
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type WBSCL_CLAMP_LOWER_Y_RGB;\
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type WBSCL_CLAMP_UPPER_CBCR;\
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type WBSCL_CLAMP_LOWER_CBCR;\
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type WBSCL_OUTSIDE_PIX_STRATEGY;\
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type WBSCL_BLACK_COLOR_G_Y;\
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type WBSCL_BLACK_COLOR_B_CB;\
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type WBSCL_BLACK_COLOR_R_CR;\
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type WBSCL_DEBUG;\
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type WBSCL_TEST_DEBUG_INDEX;\
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type WBSCL_TEST_DEBUG_WRITE_EN;\
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type WBSCL_TEST_DEBUG_DATA;\
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type WIDTH_WARMUP;\
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type HEIGHT_WARMUP;\
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type GMC_WARM_UP_ENABLE;\
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type DATA_VALUE_WARMUP;\
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type MODE_WARMUP;\
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type DATA_DEPTH_WARMUP; \
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struct dcn20_dwbc_registers {
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/* DCN2.0 */
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uint32_t WB_ENABLE;
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uint32_t WB_EC_CONFIG;
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uint32_t CNV_MODE;
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uint32_t CNV_WINDOW_START;
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uint32_t CNV_WINDOW_SIZE;
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uint32_t CNV_UPDATE;
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uint32_t CNV_SOURCE_SIZE;
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uint32_t CNV_TEST_CNTL;
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uint32_t CNV_TEST_CRC_RED;
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uint32_t CNV_TEST_CRC_GREEN;
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uint32_t CNV_TEST_CRC_BLUE;
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uint32_t WB_DEBUG_CTRL;
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uint32_t WB_DBG_MODE;
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uint32_t WB_HW_DEBUG;
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uint32_t CNV_TEST_DEBUG_INDEX;
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uint32_t CNV_TEST_DEBUG_DATA;
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uint32_t WB_SOFT_RESET;
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uint32_t WBSCL_COEF_RAM_SELECT;
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uint32_t WBSCL_COEF_RAM_TAP_DATA;
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uint32_t WBSCL_MODE;
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uint32_t WBSCL_TAP_CONTROL;
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uint32_t WBSCL_DEST_SIZE;
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uint32_t WBSCL_HORZ_FILTER_SCALE_RATIO;
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uint32_t WBSCL_HORZ_FILTER_INIT_Y_RGB;
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uint32_t WBSCL_HORZ_FILTER_INIT_CBCR;
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uint32_t WBSCL_VERT_FILTER_SCALE_RATIO;
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uint32_t WBSCL_VERT_FILTER_INIT_Y_RGB;
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uint32_t WBSCL_VERT_FILTER_INIT_CBCR;
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uint32_t WBSCL_ROUND_OFFSET;
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|
uint32_t WBSCL_OVERFLOW_STATUS;
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|
uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS;
|
|
uint32_t WBSCL_TEST_CNTL;
|
|
uint32_t WBSCL_TEST_CRC_RED;
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|
uint32_t WBSCL_TEST_CRC_GREEN;
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|
uint32_t WBSCL_TEST_CRC_BLUE;
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uint32_t WBSCL_BACKPRESSURE_CNT_EN;
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|
uint32_t WB_MCIF_BACKPRESSURE_CNT;
|
|
uint32_t WBSCL_CLAMP_Y_RGB;
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|
uint32_t WBSCL_CLAMP_CBCR;
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|
uint32_t WBSCL_OUTSIDE_PIX_STRATEGY;
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|
uint32_t WBSCL_OUTSIDE_PIX_STRATEGY_CBCR;
|
|
uint32_t WBSCL_DEBUG;
|
|
uint32_t WBSCL_TEST_DEBUG_INDEX;
|
|
uint32_t WBSCL_TEST_DEBUG_DATA;
|
|
uint32_t WB_WARM_UP_MODE_CTL1;
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|
uint32_t WB_WARM_UP_MODE_CTL2;
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|
};
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|
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struct dcn20_dwbc_mask {
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DWBC_REG_FIELD_LIST_DCN2_0(uint32_t)
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|
};
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|
|
|
struct dcn20_dwbc_shift {
|
|
DWBC_REG_FIELD_LIST_DCN2_0(uint8_t)
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};
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|
|
|
struct dcn20_dwbc {
|
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struct dwbc base;
|
|
const struct dcn20_dwbc_registers *dwbc_regs;
|
|
const struct dcn20_dwbc_shift *dwbc_shift;
|
|
const struct dcn20_dwbc_mask *dwbc_mask;
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|
};
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|
|
|
void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
|
|
struct dc_context *ctx,
|
|
const struct dcn20_dwbc_registers *dwbc_regs,
|
|
const struct dcn20_dwbc_shift *dwbc_shift,
|
|
const struct dcn20_dwbc_mask *dwbc_mask,
|
|
int inst);
|
|
|
|
bool dwb2_disable(struct dwbc *dwbc);
|
|
|
|
bool dwb2_is_enabled(struct dwbc *dwbc);
|
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|
|
void dwb2_set_stereo(struct dwbc *dwbc,
|
|
struct dwb_stereo_params *stereo_params);
|
|
|
|
void dwb2_set_new_content(struct dwbc *dwbc,
|
|
bool is_new_content);
|
|
|
|
void dwb2_config_dwb_cnv(struct dwbc *dwbc,
|
|
struct dc_dwb_params *params);
|
|
|
|
void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
|
|
|
|
bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
|
|
uint32_t src_height,
|
|
uint32_t dest_height,
|
|
struct scaling_taps num_taps,
|
|
enum dwb_subsample_position subsample_position);
|
|
|
|
bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
|
|
uint32_t src_width,
|
|
uint32_t dest_width,
|
|
struct scaling_taps num_taps);
|
|
|
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#endif
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